Abstract
CPU cache memories are small, high performance associatively accessed memories used to hold currently active portions of the main memory contents. The high ratio of CPU speed to main memory speed makes effective cache design crucial to machine performance.
In this paper, we discuss the components of cache performance, including miss ratio and access time, describe a typical cache design, and then provide a brief overview of the various design choices for cache memories including cache size and location, line (block) size, fetch algorithm, organization, main memory update policy, split vs. unified cache, multi-cache consistency and input/output, virtual vs. real addressing, replacement algorithm, TLB design, error detection and correction, pipelining and arbitration. We then review some factors of particular applicability to the TRON design.
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Bibliography
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© 1987 Springer-Verlag Tokyo
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Smith, A.J. (1987). Design Considerations for TRON Cache Memories. In: Sakamura, K. (eds) TRON Project 1987 Open-Architecture Computer Systems. Springer, Tokyo. https://doi.org/10.1007/978-4-431-68069-7_18
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DOI: https://doi.org/10.1007/978-4-431-68069-7_18
Publisher Name: Springer, Tokyo
Print ISBN: 978-4-431-68071-0
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