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Responsiveness and Timing

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VLSI Design and Test for Systems Dependability

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Abstract

This chapter deals with the issue of timing and synchronicity, which is fundamental in the architecture design of computer, communication, and control systems. In fact, if a signal took too long to travel from one point in a system to another exceeding the predetermined length of time, then the system would involve an error, fault, or failure. An electromechanical robot would lose intended integrity in coordinated limb motions without responsive signals arriving in time from elsewhere in its distributed hard real-time control system. Successful delivery of a universal clock signal would be indispensable for distributed coupled computer-and-communication systems for real-time financial transactions. Section 9.1 describes the requirements in hard real-time control system such as industrial and humanoid robots. Section 9.2 is a proposal of a computer architecture for hard real-time control that is capable of pre-emptive multiple-thread computation on demand and noise-immune communications between distributed sensor–actuator nodes. This architecture, called RMTP (Real-Time Multithread Processor), has been implemented in compact 3-D modules and made available for academic uses along with the design tools. Section 9.3 describes asynchronous networks which can efficiently and reliably connect on-chip and off-chip functions in a distributed system against timing errors. The use of a global synchronization in public wireless telecommunication is proposed in Sect. 9.4 to provide dependable connectivity and maximized throughput using the satellites and cellular base stations with heterogeneous air interfaces.

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Notes

  1. 1.

    The “chip” is a pulse of a direct-sequence spread spectrum (DSSS) code.

References

  1. IEC 61508 ed2.0, Functional safety of electrical/electronic/programmable electronic safety-related systems (2010)

    Google Scholar 

  2. H. Kopetz, Real-Time Systems, 2nd edn. (Springer, 2011)

    Google Scholar 

  3. A. Namiki, Y. Nakabo, I. Ishii, M. Ishikawa, 1 ms Sensory-motor fusion system. IEEE Trans. Mechatron. 5(3), 244–252 (2000)

    Article  Google Scholar 

  4. Y. Nakabo, I. Ishii, M. Ishikawa, 1 ms target tracking system using a massively parallel processing vision. J. Robot. Soc. Japan 15(3), 105–109 (1997)

    Article  Google Scholar 

  5. G.C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications (Springer, 2004)

    Google Scholar 

  6. K. Suito, R. Ueda, K. Fujii, T. Kogo, H. Matsutani, N. Yamasaki, Dependable responsive multithreaded processor for distributed real-time systems. IEEE Micro. 32(6), 52–61 (2012)

    Article  Google Scholar 

  7. N. Yamasaki, Responsive link for distributed real-time processing, in Proceedings of the 10th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2007), pp. 20–29

    Google Scholar 

  8. J. Urata, Y. Nakanishi, K. Okada, M. Inaba, Design of high torque and high speed leg module for high power humanoid, in Proceedings of the 2010 IEEE/RSJ International Conference on Intelligent Robots and Systems (2010), pp. 4497–4502

    Google Scholar 

  9. H. Takada, μITRON 4.0 Specification (TRON Institute, 2004)

    Google Scholar 

  10. C.L. Liu, J.W. Layland, Scheduling algorithms for multiprogramming in a hard real-time environment. J. ACM 20(1), 46–61 (1973)

    Article  MathSciNet  Google Scholar 

  11. N. Yamasaki, Responsive multithreaded processor for distributed real-time systems. J. Robot. Mechatron. 17(2), 130–141 (2005)

    Article  MathSciNet  Google Scholar 

  12. J.W.S. Liu, Real-Time Systems (Prentice Hall, 2000)

    Google Scholar 

  13. N. Yamasaki, I. Magaki, T. Itou, Prioritized SMT architecture with IPC control method for real-time processing, in Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium (IEEE, 2007), pp. 12–21

    Google Scholar 

  14. J.G. Ziegler, N.B. Nichols, Optimum settings for automatic controlles. ASME Trans. 64(11), 759–768 (1942)

    Google Scholar 

  15. T. Itou, N. Yamasaki, Design and implementation of the multimedia operation mechanism for responsive multithreaded processor. J. Robot. Mechatron. 17(4), 456–462 (2005)

    Article  Google Scholar 

  16. M. Dean, T. Williams, D. Dill, Efficient self-timing with level-encoded 2-phase dual-rail (LEDR), in Advanced Research in VLSI, ed. by C.H. Séquin (MIT Press, 1991), pp. 55–70

    Google Scholar 

  17. M. Imai, T. Yoneda, Improving dependability and performance of fully asynchronous on-chip networks, in Proceedings of ASYNC2011 (2011), pp. 65–76

    Google Scholar 

  18. R. Dobkin, R. Ginosar, A. Kolodny, Qnoc synchronous router. integration. VLSI J. 42(2), 103–115 (2009)

    Article  Google Scholar 

  19. Y. Thonnart, P. Vivet, F. Clermidy, A fully-asynchornous low-power framework for gals NOC integration, in Proceedings of DATE (2010), pp. 33–38

    Google Scholar 

  20. M.N. Horak, S.M. Nowick, M. Carlberg, U. Vishkin, A low-overhead asynchronous interconnection network for gals chip multiprocessors, in Proceedings of NOCS (2010), pp. 43–50

    Google Scholar 

  21. T. Yoneda, M. Imai, N. Onizawa, A. Matsumoto, T. Hanyu, Multi-chip NoCs for automotive applications, in Proceedings of PRDC (2012), pp. 105–110

    Google Scholar 

  22. M. Singh, S.M. Nowick, MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines, in Proceedings International Conference Computer Design (ICCD) (Nov 2001), pp. 9–17

    Google Scholar 

  23. A.J. Martin, Programming in VLSI: from communicating processes to delay-insensitive circuits, in Developments in Concurrency and Communication, UT Year of Programming Series, ed. by C.A.R. Hoare (Addison-Wesley, 1990), pp. 1–64

    Google Scholar 

  24. C. Myers, Asynchronous Circuit Design (Wiley, 2001)

    Google Scholar 

  25. M. Imai, T. Yoneda, T. Nanya, N-way ring and square arbiters. in Proceedings of the ICCD’09 (2009), pp. 125–130

    Google Scholar 

  26. G. Miorandi, D. Bertozzi, S.M. Nowick, Increasing impartiality and robustness in high- performance n-way asynchronous arbiters, in Proceedings of ASYNC (2015), pp. 108–115

    Google Scholar 

  27. K. Tsubouchi, Extended dependable air: heterogeneous wireless network for surface, space and sea, in Asia-Pacific Microwave Conference 2014 (APMC2014) (Nov 2014 (invited))

    Google Scholar 

  28. T. Takahashi, Y. Miyake, F. Yamagata, H. Oguma, S. Kameda, N. Suematsu, T. Takagi, K. Tsubouchi, Large-capacity QZSS location and short message system using frame slotted ALOHA with flag method, in IEEE 24rd International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC2013) (London, U.K., Sept 2013), pp. 3280–3285

    Google Scholar 

  29. A. Taira, Y. Miyake, S. Kameda, N. Suematsu, T. Takagi, K. Tsubouchi, QZSS location and short message communication system against big disasters, in Vietnam-Japan International Symposium on Antennas and Propagation (VJISAP2013) (Jan 2014 (invited)), pp. 229–234

    Google Scholar 

  30. A. Taira, Y. Miyake, S. Kameda, N. Suematsu, T. Takagi, K. Tsubouchi, System stability of SS-CDMA location and short message communication using QZSS, in Asia-Pacific Microwave Conference 2014 (APMC2014) (Nov 2014)

    Google Scholar 

  31. Y. Miyake, S. Kameda, A. Taira, K. Norishima, H. Oguma, N. Suematsu, T. Takagi, K. Tsubouchi, Experimental evaluation of timing synchronization accuracy consider elevation angle mask for QZSS SS-CDMA short message communication, in IEICE Technical Report, vol. 115, no. 2, RCS2015-10 (April 2015), pp. 47–52 (in Japanese)

    Google Scholar 

  32. N. Suematsu, S. Kameda, Y. Miyake, T. Takahashi, A. Taira, T. Takagi, K. Tsubouchi, QZSS SS-CDMA location and short message communication system, in 2015 Vietnam-Japan MicroWave 2015 (VJMW2015) (Ho Chi Minh City, Vietnum, Aug 2015 (invited))

    Google Scholar 

  33. K. Ohya, S. Kameda, H. Oguma, A. Taira, N. Suematsu, T. Takagi, K. Tsubouchi, Experimental evaluation of timing synchronization accuracy for QZSS short message synchronized SS-CDMA communication, in 2016 IEEE 27th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2016) (Sept 2016)

    Google Scholar 

  34. FURUNO ELECTRIC CO., LTD., GF-180TC, http://www.furuno.com/en/products/gnss-module/GF-180TC

  35. CORE CORPORATION, CD311, http://www.core.co.jp/product/gnss/outline/qzs_gps.html

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Author information

Authors and Affiliations

  1. National Institute of Informatics, Tokyo, Japan

    Tomohiro Yoneda

  2. National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan

    Yoshihiro Nakabo

  3. Keio University, Yokohama, Japan

    Nobuyuki Yamasaki & Masayoshi Takasu

  4. Hirosaki University, Hirosaki, Japan

    Masashi Imai

  5. Tohoku University, Sendai, Japan

    Suguru Kameda, Akinori Taira, Noriharu Suematsu, Tadashi Takagi & Kazuo Tsubouchi

  6. National Institute of Technology, Toyama College, Toyama, Japan

    Hiroshi Oguma

Authors
  1. Tomohiro Yoneda
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  2. Yoshihiro Nakabo
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  3. Nobuyuki Yamasaki
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  4. Masayoshi Takasu
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  5. Masashi Imai
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  6. Suguru Kameda
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  7. Hiroshi Oguma
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  8. Akinori Taira
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  9. Noriharu Suematsu
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  10. Tadashi Takagi
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  11. Kazuo Tsubouchi
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Correspondence to Tomohiro Yoneda .

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Editors and Affiliations

  1. Rigaku Corporation, Tokyo, Japan

    Shojiro Asai

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Yoneda, T. et al. (2019). Responsiveness and Timing. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_9

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  • DOI: https://doi.org/10.1007/978-4-431-56594-9_9

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  • Publisher Name: Springer, Tokyo

  • Print ISBN: 978-4-431-56592-5

  • Online ISBN: 978-4-431-56594-9

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