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Time-Dependent Degradation in Device Characteristics and Countermeasures by Design

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VLSI Design and Test for Systems Dependability

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Abstract

Advancement of process technologies has significantly improved the performance of semiconductor devices and consequently of circuits. Device lifetime, on the other hand, has been unavoidably compromised through the introductions of new materials, new process technologies, etc. Mitigating measures against transient degradation of circuit performance are now what all circuit designers should know. In this chapter, techniques to monitor device degradation are introduced. By periodic monitoring, functional failures induced after fabrication can be detected. Practical circuit designs that mitigate, predict, diagnose, and recover from faults in the running systems are proposed to achieve an ultimate design goal of realizing dependable VLSIs.

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References

  1. R. Degraeve, G. Groeseneken, R. Bellens, J.L. Ogier, M. Depas, P.J. Roussel, H.E. Maes, New insights in the relation between electron trap generation and the statistical properties of oxide breakdown. IEEE Trans. Electron Devices 45(4), 904–911 (1998)

    Article  Google Scholar 

  2. B. Kaczer, R. Degraeve, M. Rasras, K.V. de Mieroop, P.J. Roussel, G. Groeseneken, Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability. IEEE Trans. Electron Devices 49(3), 500–506 (2002)

    Article  Google Scholar 

  3. M. Depas, T. Nigam, M.M Heyns, Soft breakdown of ultra-thin gate oxide layers. IEEE Trans. Electron Devices 43(9), 1499–1504 (1996)

    Google Scholar 

  4. K. Okada, Extended time dependent dielectric breakdown model based on anomalous gate area dependence of lifetime in ultra think silicon dioxides. Japan. J. Appl. Phys. 36(3B), 1443–1447 (1997)

    Google Scholar 

  5. A. Popa, An injection level dependent theory of the MOS transistor in saturation. IEEE Trans. Electron Devices 19(6), 774–781 (1972)

    Article  Google Scholar 

  6. P.E. Cottrell, R.R. Troutman, T.H. Ning, Hot-electron emission in n-channel IGFET’s. IEEE Trans. Electron Devices 26(4), 520–533 (1979)

    Article  Google Scholar 

  7. C. Hu, Lucky-electron model of channel hot electron emission. IEDM Tech. Dig. 25, 22–25 (1979)

    Google Scholar 

  8. S. Mahapatra, C. Parikh, V. Rao, C.R. Viswanathan, J. Vasi, Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFET’s. IEEE Trans. Electron Device 47(4), 789–796 (2000)

    Google Scholar 

  9. J.H. Stathis, S. Zafar, The negative bias temperature instability in MOS devices. Rev. Microelectron. Reliab. 46(2–4), 270–286 (2006)

    Google Scholar 

  10. S.E. Rauch, Review and reexamination of reliability effects related to NBTI-induced statistical variations. IEEE Trans. Device Mater. Reliab. 7(4), 524–529 (2007)

    Article  Google Scholar 

  11. T. Grasser, B. Kaczer, W. Goes, An energy-level perspective of bias temperature instability, in Proceedings of International Reliability Physics Symposium (IRPS) (April 2008), pp. 28–38

    Google Scholar 

  12. P.B. Ghate, Electromigration-induced failures in VLSI interconnects, in Annual Reliability Physics Symposium (IEEE, 1982), pp. 292–299

    Google Scholar 

  13. D. Pierce, P. Brusius, Reliability physics of advanced electron devices electromigration. Rev. Microelectron. Reliab. 37(7), 1053–1072 (1997)

    Article  Google Scholar 

  14. J.R. Black, Electromigration failure modes in aluminum metallization for semiconductor devices. Proc. IEEE 57(9), 1587–1594 (1969)

    Article  Google Scholar 

  15. J. Yue, W. Funsten, R. Taylor, Stress induced voids in aluminum interconnects during IC processing, in Annual Reliability Physics Symposium (IEEE, 1985), pp. 126–137

    Google Scholar 

  16. T.H. Kim, R. Persaud, C.H. Kim, Silicon odometer: an on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE J. Solid-State Circ. 43(4), 874–880 (2008)

    Article  Google Scholar 

  17. T. Sato, T. Kozaki, T. Uezono, H. Tsutsui, H. Ochi, A device array for efficient bias-temperature instability measurements, in Proceedings of European Solid-State Device Research Conference (ESSDERC) (2011), pp. 143–146

    Google Scholar 

  18. H. Awano, M. Hiromoto, T. Sato, BTIarray: a time-overlapping transistor array for efficient statistical characterization of bias temperature instability. IEEE Trans. Device Mater. Reliab. 14(3), 833–843 (2014)

    Article  Google Scholar 

  19. J.B. Velamala, K.B. Sutaria, T. Sato, Y. Cao, Physics matters: statistical aging prediction under trapping/detrapping, in Proceedings of ACM/IEEE Design Automation Conference (DAC) (June 2012), pp. 139–144

    Google Scholar 

  20. P. Singh, E. Karl, D. Sylvester, D. Blaauw, Dynamic NBTI management using a 45 nm multi-degradation sensor, in IEEE Custom Integrated Circuits Conference (Sept 2010), pp. 1–4

    Google Scholar 

  21. P.F. Lu, K.A. Jenkins, A built-in BTI monitor for long-term data collection in IBM microprocessors, in Proceedings of International Reliability Physics Symposium (IRPS) (Apr 2013), pp. 4A.1.1–4A.1.6

    Google Scholar 

  22. H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye, Adaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(2), 333–343 (2012)

    Article  Google Scholar 

  23. S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye, Stochastic error rate estimation for adaptive speed control with field delay testing, in IEEE International Conference on Computer Aided Design (Nov 2013), pp. 107–114

    Google Scholar 

  24. F. Masuoka et al., A new flash E2PROM cell using triple polysilicon technology, in IEEE International Electron Devices Meeting (IEDM) (1984), pp. 465–467

    Google Scholar 

  25. F. Masuoka et al., New ultra high density EPROM and flash EEPROM with NAND structure cell, in IEEE International Electron Devices Meeting (IEDM) (1987), pp. 552–555

    Google Scholar 

  26. F. Masuoka, Great encounters leading me to the inventions of flash memories and surrounding gate transistor technology. IEEE Solid-State Circ. Mag. 10–20 (2013)

    Google Scholar 

  27. S. Aritome, NAND flash innovations. IEEE Solid-State Circ. Mag. 21–29 (2013)

    Google Scholar 

  28. M. Bauer et al., A multilevel-cell 32 Mb flash memory, in IEEE International Solid-State Circuits Conference (ISSCC) (1995), 132–133

    Google Scholar 

  29. K. Takeuchi et al., A 56 nm CMOS 99 mm2 8 Gb Multi-level NAND flash memory with 10 MB/s program throughput, in IEEE International Solid-State Circuits Conference (ISSCC) (2006), pp. 144–145

    Google Scholar 

  30. R. Cernea et al., A 34 MB/s-program-throughput 16 Gb MLC NAND with all-bitline architecture in 56 nm, in IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 420–421

    Google Scholar 

  31. R. Zeng et al., A 172 mm2 32 Gb MLC NAND flash memory in 34 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2009), pp. 236–237

    Google Scholar 

  32. H. Kim et al., A 159 mm2 32 nm 32 Gb MLC NAND-flash memory with 200 MB/s asynchronous DDR interface, in IEEE International Solid-State Circuits Conference (ISSCC) (2010), pp. 442–443

    Google Scholar 

  33. C. Lee et al., A 32 Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2010), pp. 446–447

    Google Scholar 

  34. K. Fukuda et al., A 151 mm2 64 Gb MLC NAND flash memory in 24 nm CMOS technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2011), pp. 198–199

    Google Scholar 

  35. T.-Y. Kim et al., A 32 Gb MLC NAND flash memory with Vth margin-expanding schemes in 26 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2011), pp. 202–203

    Google Scholar 

  36. N. Shibata et al., A 19 nm 112.8 mm2 64 Gb multi-level flash memory with 400 Mb/s/pin 1.8 V toggle mode interface, in IEEE International Solid-State Circuits Conference (ISSCC) (2012), pp. 422–423

    Google Scholar 

  37. M. Helm et al., A 128 Gb MLC NAND-flash device using 16 nm planar cell, in IEEE International Solid-State Circuits Conference (ISSCC) (2014), pp. 326–327

    Google Scholar 

  38. S. Choi et al., A 93.4 mm2 64 Gb MLC NAND-flash memory with 16 nm CMOS technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2014), pp. 328–329

    Google Scholar 

  39. Y. Li et al., A 16 Gb 3b/cell NAND flash memory in 56 nm with 8 MB/s write rate, in IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 506–507

    Google Scholar 

  40. S.-H. Chang et al., A 48 nm 32 Gb 8-Level NAND flash memory with 5.5 MB/s program throughput, in IEEE International Solid-State Circuits Conference (ISSCC) (2009), pp. 240–241

    Google Scholar 

  41. G.G. Marotta et al., A 3 bit/cell 322 Gb NAND flash memory at 34 nm with 6 MB/s program throughput and with dynamic 2 bit/cell blocks configuration mode for a program throughput increase up to 13 MB/s, in IEEE International Solid-State Circuits Conference (ISSCC) (2010), pp. 444–445

    Google Scholar 

  42. Y. Li et al., 128 Gb 3 bit/cell NAND flash memory in 19 nm technology with 18 MB/s write rate and 400 Mb/s toggle mode, in IEEE International Solid-State Circuits Conference (ISSCC) (2012), pp. 436–437

    Google Scholar 

  43. G. Naso et al., A 128 Gb 3b/cell NAND flash design using 20 nm planar-cell technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2013), pp. 218–219

    Google Scholar 

  44. K. Kanda et al., A 120 mm2 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology, in IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 430–431

    Google Scholar 

  45. C. Trinh et al., A 5.6 MB/s 64 Gb 4b/cell NAND flash memory in 43 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2009), pp. 246–247

    Google Scholar 

  46. D. Nobunaga et al., A 50 nm 8 Gb NAND flash memory with 100 MB/s program throughput and 200 MB/s DDR interface, in IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 426–427

    Google Scholar 

  47. http://www.itrs.net/home.html

  48. K.-T. Park et al., Three-dimensional 128 Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50 MB/s high-speed programming, in IEEE International Solid-State Circuits Conference (ISSCC) (2014), pp. 334–335

    Google Scholar 

  49. K. Takeuchi et al., A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid-State Circ. 33(8), 85–96 (2012)

    Google Scholar 

  50. K.-D. Suh et al., A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme, in IEEE International Solid-State Circuits Conference (ISSCC) (1995), pp. 128–129

    Google Scholar 

  51. J.-D. Lee et al., Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90-nm NAND flash memory cells, in IEEE International Reliability Physics Symposium (IRPS) (2003), pp. 497–501

    Google Scholar 

  52. K. Prall, Scaling non-volatile memory below 30 nm, in IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW) (2007), pp. 5–10

    Google Scholar 

  53. S.W. Park, Prospect for new memory technology. Flash Mem. Summit (2012)

    Google Scholar 

  54. J.-D. Lee et al., Effects of floating-gate interference on nand flash memory cell operation. IEEE Electron Device Lett. 23(5), 264–266 (2002)

    Article  Google Scholar 

  55. M. Park et al., Direct field effect of neighboring cell transistor on cell-to-cell interference of NAND flash cell arrays. IEEE Electron Device Lett. 30(2), 174–177 (2009)

    Article  Google Scholar 

  56. J.-D. Lee et al., A new programming disturbance phenomenon in NAND flash memory by source/drain hot-electrons generated by GIDL current, in IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW) (2006), pp. 31–33

    Google Scholar 

  57. S. Aritome et al., Novel negative Vt shift phenomenon of program-inhibit cell in 2X-3X-nm self-aligned STI NAND flash memory. IEEE Trans. Electron Devices 59(11), 2950–2955 (2012)

    Article  Google Scholar 

  58. Y.S. Kim et al., New scaling limitation of the floating gate cell in NAND flash memory, in IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 599–603

    Google Scholar 

  59. K. Prall, K. Parat, 25 nm 64 Gb MLC NAND technology and scaling challenges, in IEEE International Electron Devices Meeting (IEDM) (2010), pp. 102–105

    Google Scholar 

  60. K.-T. Park et al., A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories. IEEE J. Solid-State Circ. 43(4), 919–928 (2008)

    Article  Google Scholar 

  61. N. Mielke et al., Bit error rate in NAND flash memories, in IEEE International Reliability Physics Symposium (IRPS) (2008), pp. 9–19

    Google Scholar 

  62. E. Yaakobi et al., Error characterization and coding schemes for flash memories, in IEEE Global Communications Conference, Exhibition & Industry Forum (GLOBECOM) (2010), pp. 1856–1860

    Google Scholar 

  63. R. Motwani et al., Low density parity check (LDPC) codes and the need for stronger ECC. Flash Mem. Summit (2011)

    Google Scholar 

  64. H. Parizi, Flash reliablity, beyond data management and ECC. Flash Mem. Summit (2013)

    Google Scholar 

  65. S. Tanakamaru et al., Error-prediction LDPC and error-recovery schemes for highly reliable solid-state drives (SSDs). IEEE J. Solid-State Circ. 48(11), 2920–2933 (2013)

    Article  Google Scholar 

  66. G. Dong et al., On the Use of soft-decision error-correction codes in NAND flash memory. IEEE Trans. Circ. Syst. I 58(2), 429–439 (2011)

    MathSciNet  Google Scholar 

  67. D.A. Patterson et al., A case for redundant arrays of inexpensive disks (RAID), in ACM Special Interest Group on Management of Data (SIGMOD) (1988), pp. 108–116

    Google Scholar 

  68. M. Blaum et al., EVENODD: an efficient scheme for tolerating double disk failures in RAID architectures. IEEE Trans. Comput. 44(2), 192–202 (1995)

    Article  Google Scholar 

  69. M. Balakrishnan et al., Differential RAID: rethinking RAID for SSD reliability, in European Conference on Computer Systems (2010)

    Google Scholar 

  70. D.-H. Lee, W. Sung, Least squares based cell-to-cell interference cancelation technique for multi-level cell NAND flash memory, in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) (2012), pp. 1601–1604

    Google Scholar 

  71. R. Motwani, Architecture customized constrained coding for mitigating FGFG coupling in flash. Flash Mem. Summit (2011)

    Google Scholar 

  72. S. Tanakamaru et al., Highly reliable and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming. IEEE J. Solid-State Circ. 47(1), 85–96 (2012)

    Article  Google Scholar 

  73. International Technology Roadmap for Semiconductors (2013), http://www.itrs.net/

  74. W. Wang et al., Compact modeling and simulation of circuit reliability for 65-nm CMOS technology. IEEE Trans. Device Mater. Reliab. 7(4), 509–517 (2007)

    Google Scholar 

  75. International Electrotechnical Commission, IEC61508, Functional safety of electrical/ electronic/ programmable electronic safety-related systems, Ed.2.0 (2010-4), http://www.iec.ch/functionalsafety/

  76. ISO26262 Road vehicles -Functional safety-, First Edition, 2011-11

    Google Scholar 

  77. N. Kanekawa et al., Dependability in Electronic Systems (Springer, 2010). ISBN 978-1-4419-6714-5

    Google Scholar 

  78. Y. Sato et al., DART: dependable VLSI test architecture and its implementation. in Proceedings International Test Conference, paper 15.2 (2012)

    Google Scholar 

  79. Y. Miura et al., On-chip temperature and voltage measurement for field testing, in Proceedings of European Test Symposium (2012), p. 204

    Google Scholar 

  80. R. Franch, P. Restle, N. James, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K.V. Goor, G. Salem, On-chip timing uncertainty measurement on IBM microprocessors, in Proceedings of International Test Conference (2007), pp. 1.1.1–1.1.7

    Google Scholar 

  81. M.-C. Tsai, C.-H. Cheng, C.-M. Yang, An all-digital high-precision built-in delay time measurement circuit, in Proceedings of IEEE VLSI Test Symposium (2008), pp. 249–254

    Google Scholar 

  82. R. Tayade, J.A. Abraham, On-chip programmable capture for accurate path delay test and characterization, in Proceedings of International Test Conference (2008), pp. 6.2.1–6.2.10

    Google Scholar 

  83. X. Wang, M. Techranipoor, R. Datta, A novel architecture for on-chip path delay measurement, in Proceedings of International Test Conference (2009), pp. 12.1.1–12.1.10

    Google Scholar 

  84. X. Wang, M. Tehranipoor, R. Datta, Path-RO: a novel on-chip critical path delay measurement under process variations, in Proceedings of International Conference on Computer-Aided Design (Nov 2008), pp. 640–646

    Google Scholar 

  85. M. Nicolaidis, Y. Zorian, On-line testing for VLSI-A compendium of approaches. J. Electron. Test. Theory and Applications 12(1–2), 7–20 (1998)

    Article  Google Scholar 

  86. H. Al-Asaad et al., Online BIST for Embedded Systems. IEEE Des. Test Comput. 15(4), 17–24 (1998)

    Article  Google Scholar 

  87. J. Qian et al., Logic BIST architecture for system-level test and diagnosis, in Proceedings of Asian Test Symposium (2009), pp. 21–28

    Google Scholar 

  88. Y. Li, S. Makar, S. Mitra, CASP: concurrent autonomous chip self-test using stored test patterns, in Proceedings of Design Automation and Test in Europe (2008), pp. 885–89

    Google Scholar 

  89. H. Inoue et al., VAST: virtualization-assisted concurrent autonomous self-test, in Proceedings of International Test Conference, paper 12.3 (2008)

    Google Scholar 

  90. Y. Sato et al., A stochastic model for NBTI-induced LSI degradation in field, in IEEE Asian Test Symposium (2013), pp. 183–188

    Google Scholar 

  91. D. Ernst, N.S. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge, K. Flautner, Razor: a low-power pipeline based on circuit-level timing speculation, in Proceedings of International Symposium on Microarchitecture (Dec 2003), pp. 7–18

    Google Scholar 

  92. T. Sato, Y. Kunitake, A simple flip-flop circuit for typical-case designs for DFM, in Proceedings of International Symposium on Quality Electronic Design (Mar 2007), pp. 539–544

    Google Scholar 

  93. Y. Sato et al., Reduction of NBTI-induced degradation on ring oscillators in FPGA, in Proceedings of 20th Pacific Rim International Symposium on Dependable Computing (2014), pp. 59–67

    Google Scholar 

  94. K. Itoh, Adaptive circuits for the 0.5-V nanoscale CMOS era, in IEEE International Solid-State Circuits Conference (Feb 2009), pp. 14–20

    Google Scholar 

  95. S. Borkar, T. Karnik, V. De, Design and reliability, in Proceedings of Design Automation Conference (June 2004), p. 75

    Google Scholar 

  96. C. Wilkerson, H. Gao, A.R. Alameldeen, Z. Chishti, M. Khellah, S.-L. Lu, Trading off cache capacity for reliability to enable low voltage operation, in Proceedings of International Symposium on Computer Architecture (June 2008), pp. 203–214

    Google Scholar 

  97. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, M. Yoshimoto, A 7T/14T dependable SRAM and its array structure to avoid half selection, in Proceedings of International Conference on VLSI Design (Jan 2009), pp. 295–300

    Google Scholar 

  98. E. Seevinick, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circ. 22(5), 748–754 (1987)

    Article  Google Scholar 

  99. E. Grossar, M. Stucchi, K. Maex, W. Dehaene, Statically aware SRAM memory array design, in Proceedings of International Symposium on Quality Electronic Design (Mar 2006), pp. 6–30

    Google Scholar 

  100. N. Binkert, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)

    Article  Google Scholar 

  101. Standard Performance Evaluation Corporation, The SPEC CPU 2006 Benchmark Suite. http://www.specbench.org

  102. J. Yao, S. Okada, H. Shimada, K. Kobayashi, Y. Nakashima, DARA: a low-cost reliable architecture based on unhardened devices and its case study of radiation stress test, in NSREC’12 (July 2012)

    Google Scholar 

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Authors and Affiliations

  1. Kyoto University, Kyoto, Japan

    Takashi Sato

  2. Osaka University, Suita, Japan

    Masanori Hashimoto

  3. Chuo University, Tokyo, Japan

    Shuhei Tanakamaru & Ken Takeuchi

  4. Kyushu Institute of Technology, Iizuka, Japan

    Yasuo Sato & Seiji Kajihara

  5. Kobe University, Kobe, Japan

    Masahiko Yoshimoto, Jinwook Jung, Yuta Kimi & Hiroshi Kawaguchi

  6. Nagoya University, Nagoya, Japan

    Hajime Shimada

  7. Huawei Technologies, Beijing, China

    Jun Yao

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  1. Takashi Sato
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  2. Masanori Hashimoto
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  3. Shuhei Tanakamaru
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Correspondence to Takashi Sato .

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    Shojiro Asai

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Sato, T. et al. (2019). Time-Dependent Degradation in Device Characteristics and Countermeasures by Design. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_6

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