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Variations in Device Characteristics

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VLSI Design and Test for Systems Dependability

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Abstract

Ever increasing variability in device characteristics is a major threat to the dependability, since it could give rise to faults and failures in VLSI circuits and systems. The variability arises from the variation in device parameters , such as geometry and doping densities, that is inherently associated with the technology scaling . This chapter deals with the variability of scaled devices and countermeasures to enhance dependability both at the device and circuit levels. First, in Sect. 5.1, variations in transistor characteristics are overviewed with measured variability from 0.35 μm down to 40 nm technologies. The rapid increase in within-die random variations is clearly shown. Possible scaling scenarios, which are device-level strategies to reduce variability, are explained. In the following sections, we discuss countermeasure techniques at the circuit level. In Sect. 5.2, on-chip monitor circuits for variability measurement and performance compensation by localized body biasing are proposed and verified by silicon measurements. In Sects. 5.3 and 5.4, two techniques for predicting and preventing timing faults during runtime are introduced. The first technique in Sect. 5.3 relies on accurate delay-time measurement by an on-chip monitor circuit. Timing margins reduced by aging effects such as negative-bias-temperature instability (NBTI) can be evaluated and compensated. The second technique in Sect. 5.4 proposes a warning flip-flop that can predict possible timing errors before they actually happen, thus enables dependable operation throughout the whole life cycle of the circuit. Finally in Sect. 5.5, variability-aware circuit architectures are discussed for Static Random Access Memories (SRAMs). The proposed SRAM achieves expanded operating margins by fine-grain assist bias control at low supply voltages.

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Notes

  1. 1.

    Part of this work was done while the author was with Fukuoka University, Japan.

  2. 2.

    Part of this work was done while the author was with Kyushu University, Japan.

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Acknowledgments

This work was supported in part by JST CREST DVLSI project, by JSPS Grant-in-Aid for Exploratory Research, and by the fund from Central Research Institute of Fukuoka University. It was also supported by VDEC of the University of Tokyo in collaboration with Synopsys Inc., Cadence Design Systems Inc., and Rohm Co. Ltd. The cell library used in this research was developed by Tamaru and Onodera laboratory, Kyoto University and is released by Kazutoshi Kobayashi of Kyoto Institute of Technology. The authors sincerely appreciate Shunitsu Kohara of Toshiba Corporation for helping them use MeP simulator.

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Authors and Affiliations

  1. Kyoto University, Kyoto, Japan

    Hidetoshi Onodera

  2. Tokyo Metropolitan University, Hino, Japan

    Yukiya Miura

  3. Kyushu Institute of Technology, Iizuka, Japan

    Yasuo Sato & Seiji Kajihara

  4. Fukuoka University, Fukuoka, Japan

    Toshinori Sato

  5. Tokyo Institute of Technology, Tokyo, Japan

    Ken Yano

  6. Panasonic Corporation, Kadoma, Japan

    Yuji Kunitake

  7. Renesas Electronics Corporation, Tokyo, Japan

    Koji Nii

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  1. Hidetoshi Onodera
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  2. Yukiya Miura
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  3. Yasuo Sato
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  5. Toshinori Sato
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Correspondence to Hidetoshi Onodera .

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    Shojiro Asai

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Onodera, H. et al. (2019). Variations in Device Characteristics. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_5

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  • DOI: https://doi.org/10.1007/978-4-431-56594-9_5

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