Abstract
Current automotive electronic systems contain many ECUs (Electronic Control Units), and many of them play very important roles for safety-critical applications. However, in conventional ECU configurations, each ECU is usually tied to specific functions, and is connected to specific sensors/actuators. Thus, failure of an ECU directly leads to loss of the function related to the ECU. A centralized ECU approach has potential to resolve these issues. In this configuration, since any ECU can access any intelligent sensor/actuator and each function can be executed by any ECU, a faulty ECU no longer results in malfunction of specific functions that are assigned to it. This chapter introduces a dependable NoC (Network-on-Chip) platform that is suitable for a centralized ECU. In this platform, asynchronous design style is used to design on-/off-chip network to handle delay faults or process and other variations. Especially, for achieving the performance compatibility between on-/off-chip data transmissions, current-mode circuitry is applied. For mitigating router or link faults, a dependable routing algorithm is adopted. Finally, its dependable task execution scheme makes the platform function correctly so long as the capability of surviving processor core faults permits. The outcome of this research project has formed into an evaluation platform that includes a hardware board, a support tool for the dependable task execution scheme, and a functionality of hardware-in-the-loop simulation using a built-in plant model (please refer to Sect. 19.5 for details).
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References
T. Yoneda, M. Imai, N. Onizawa, A. Matsumoto, T. Hanyu, Multi-chip NoCs for automotive applications, in Proceedings of PRDC2012 (2012), pp. 105–110
Recomp, Reduced Certification Costs for Trusted Multi-Core Platforms, http://atc.ugr.es/recomp/
Race, Robust and Reliant Automotive Computing Environment for Future Ecars, http://projekt-race.de/
M. Dean, T. Williams, D. Dill, Efficient self-timing with level-encoded 2-phase dual-rail (LEDR), in Advanced Research in VLSI, ed. by C.H. Séquin (MIT Press, 1991), pp. 55–70
H. Shirahama, A. Mochizuki, Y. Watanabe, T. Hanyu, Energy-aware current-mode inter-chip link for a dependable gals noc platform, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2014) (2014), pp. 1865–1868
A. Mochizuki, H. Shirahama, T. Hanyu, Design of a quaternary single-ended current-mode circuit for an energy-efficient inter-chip asynchronous communication link, in Proceedings of 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL2014) (2014), pp. 67–72
A. Mochizuki, H. Shirahama, Y. Watanabe, T. Hanyu, Design of an energy-efficient ternary current-mode intra-chip communication link for an asynchronous network-on-chip. IEICE Trans. Inf. Syst. E97-D(9), (2014)
W. Dally, B. Towles, Principles and Practices of Interconnection Networks, (Morgan Kaufmann Publishers, 2003)
D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, D. Blaauw, Highly resilient routing algorithm for fault-tolerant NoCs, in Proceedings of DATE09 (2009), pp. 21–26
P.-H. Sui, S.-D. Wang, Fault-tolerant wormhole routing algorithm for mesh networks. IEE Proc. Comput. Digit. Tech. 147(1), 9–14 (2000)
J. Zhou, F. Lau, Adaptive fault-tolerant wormhole routing in 2D meshes, in Proceedings of IPDPS01 (2001)
C.J. Glass, L.M. Ni, Fault-tolerant wormhole routing in meshes. Proceedings of FTCS23 (1993), pp. 240–249
M. Imai, T. Yoneda, Improving dependability and performance of fully asynchronous on-chip networks, in Proceedings of ASYNC2011 (2011), pp. 65–76
H. Saito, T. Yoneda, Y. Nakamura, An ILP-based multiple task allocation method for fault tolerance networks-on-chip, in Proceedings of MCSoC2012 (2012), pp. 100–106
M. Imai, T. Yoneda, Fault diagnosis and reconfiguration method for network-on-chip based multiple processor systems with restricted private memories. IEICE Trans. Inf. Syst. E96-D(9), 1914–1925 (2013)
T. Yoneda, M. Imai, H. Saito, T. Hanyu, K. Kise, Y. Nakamura, An NOC-based evaluation platform for safety-critical automotive applications, in Proceedings of APCCAS2014 (2014)
Acknowledgements
This work is supported partially by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc and Cadence Design Systems, Inc.
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Yoneda, T. et al. (2019). Network-on-Chip Based Multiple-Core Centralized ECUs for Safety-Critical Automotive Applications. In: Asai, S. (eds) VLSI Design and Test for Systems Dependability. Springer, Tokyo. https://doi.org/10.1007/978-4-431-56594-9_19
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DOI: https://doi.org/10.1007/978-4-431-56594-9_19
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