Summary
In semiconductor manufacturing, discovering the processes that are attributable to defect rates is a lengthy and expensive procedure. This paper proposes a approach for understanding the impact of process variables on defect rates. By using a process-based hierarchical model, we can relate sub-process manufacturing data to layer-specific defect rates. This paper demonstrates a hierarchical modeling method using process data drawn from the Gate Contact layer, Metal 1 layer, and Electrical Test data to produce estimates of defect rates. A benefit of the hierarchical approach is that the parameters of the high-level model may be interpreted as the relative contributions of the sub-models to the overall yield. Additionally, the output from the sub-models may be monitored with a control chart that is ‘oriented’ toward yield.
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Mastrangelo, C.M., Kumar, N., Forrest, D. (2010). Hierarchical Modeling for Monitoring Defects. In: Lenz, HJ., Wilrich, PT., Schmid, W. (eds) Frontiers in Statistical Quality Control 9. Physica-Verlag HD. https://doi.org/10.1007/978-3-7908-2380-6_15
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DOI: https://doi.org/10.1007/978-3-7908-2380-6_15
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