Hierarchical Modeling for Monitoring Defects
In semiconductor manufacturing, discovering the processes that are attributable to defect rates is a lengthy and expensive procedure. This paper proposes a approach for understanding the impact of process variables on defect rates. By using a process-based hierarchical model, we can relate sub-process manufacturing data to layer-specific defect rates. This paper demonstrates a hierarchical modeling method using process data drawn from the Gate Contact layer, Metal 1 layer, and Electrical Test data to produce estimates of defect rates. A benefit of the hierarchical approach is that the parameters of the high-level model may be interpreted as the relative contributions of the sub-models to the overall yield. Additionally, the output from the sub-models may be monitored with a control chart that is ‘oriented’ toward yield.
KeywordsControl Chart Hierarchical Modeling Defect Rate Intermediate Data Statistical Quality Control
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- Friedman, D.J., Hansen, M.H., Nair, V.N. and James, D.A. (1997) Model-free estimation of defect clustering in integrated circuit fabrication. IEEE Transactions in Integrated Circuit Manufacturing 10(3): 344-359.Google Scholar
- Horton, D. (1998) Modeling the yield of mixed-technology die. Solid State Technology 41(9): 109-119.Google Scholar
- Van Zant P (2004) Microchip fabrication: a practical guide to semiconductor processing. McGraw-Hill, New York.Google Scholar