Skip to main content
SpringerLink
Log in

Adaptive Resonance Theory Microchips

  • Chapter
Innovations in ART Neural Networks

Part of the book series: Studies in Fuzziness and Soft Computing ((STUDFUZZ,volume 43))

  • 230 Accesses

Abstract

This chapter addresses implementation of learning models inspired by Adaptive Resonance Theory. A real-time clustering microchip based on the ART1 algorithm is presented, capable of classification and fast learning of 100-bit input patterns into up to 18 categories. A second chip is also presented which implements the ARTMAP algorithm for pattern association. We include experimental learning results from both prototypes, fabricated in standard single-poly double-metal 1.6μm and 1.0μm CMOS digital processes. MOS Transistors mismatch characterization is­sues are also addressed.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Mauduit, N., Duranton, M., Gobert, J., and Sirat, J.A. (1992), “Lneuro 1.0: A piece of hardware lego for building neural network systems,” IEEE Transactions on Neural Networks, Vol. 3, no. 3, pp. 414–422.

    Article  Google Scholar 

  2. Jones, S., Sammut, K., Nielsen, C, and J. Staunstrup, (1991), “Toroidal neural network: Architecture and processor granularity issues,” in VLSI Design of Neural Networks, U. Ramacher and U. Rueckert, Eds., pp. 229–254. Kluwer Academic Publishers, Dor­drecht, Netherlands.

    Chapter  Google Scholar 

  3. Ramacher, U., Beichter, J., Raab, W., Anlauf, J., Bruels, N., Hachmann, U., and Wesseling, M. (1991), “Design of a 1st generation neurocomputer,” in VLSI Design of Neural Networks, Ramacher, U. and Rueckert, U. Eds., pp. 271–310. Kluwer Academic Publishers, Dordrecht, Netherlands.

    Chapter  Google Scholar 

  4. Kohonen, T. (1989), Self-Organization and Associative Memory, Springer-Verlag, Berlin, Germany.

    Book  Google Scholar 

  5. Bezdek, J. (1981), Pattern Recognition with Fuzzy Objective Function Algorithms, Plenum, New York.

    Book  MATH  Google Scholar 

  6. Duda, R. and Hart, P. (1973), Pattern Classification and Scene Analysis, Wiley, New York.

    MATH  Google Scholar 

  7. Hartigan, J. (1975), Clustering Algorithms, Wiley, New York.

    MATH  Google Scholar 

  8. Dubes, R. and Jain, A. (1988), Algorithms that Cluster Data, Pren­tice Hall, Englewood Cliffs, NJ.

    Google Scholar 

  9. Pao, Y.H. (1989), Adaptive Recognition and Neural Networks, Addison Wesley, Reading, MA.

    MATH  Google Scholar 

  10. Rodriguez-Vazquez, A., Espejo, S., Dommguez-Castro, R., Huertas, J.L., and Sanchez-Sinencio, E. (1993), “Current-mode techniques for the implementation of continous- and discrete-time cellular neural networks,” IEEE Transactions on Circuits and Systems II, Vol 40, no. 3, pp. 132–146.

    Article  Google Scholar 

  11. Linares-Barranco, B., Sanchez-Sinencio, E., Rodriguez-Vazquez, A., and Huertas, J.L. (1993), “A CMOS analog adaptive BAM with on-chip learning and weight refreshing,” IEEE Transactions on Neural Networks, Vol. 4, no. 3, pp. 445–455.

    Article  Google Scholar 

  12. Carpenter, G.A. and Grossberg, S. (1987), “A massively parallel architecture for a self-organizing neural pattern recognition machine,” Computer Vision, Graphics, and Image Processing, Vol. 37, pp. 54–115.

    Article  MATH  Google Scholar 

  13. Serrano-Gotarredona, T. and Linares-Barranco, B. (1998), Adaptive Resonance Theory Microchips. Circuit Design Techniques, Kluwer Academic Publishers, Boston.

    Book  Google Scholar 

  14. Keulen, E., Colak, S., Withagen, H., and Hegt, H. (1994), “Neural network hardware performance criteria,” Proceedings of the 1994 Int. Conf. on Neural Networks (ICNNf 94), pp. 1885–1888.

    Google Scholar 

  15. Riedmiller, M. (1994), “Advanced supervised learning in multi­layer perceptions — from backpropagation to adaptive learning algorithms,” Int. Journal of Computer Standards and Interfaces, Vol. 5.

    Google Scholar 

  16. Kosko, B. (1987), “Adaptive bidirectional associative memories,” Applied Optics, Vol. 26, pp. 4947–4960.

    Article  Google Scholar 

  17. Wand, Y.F., Cruz, J.B., and Mulligan, J.H. (1990), “On multiple training for bidirectional associative memory,” IEEE Transactions on Neural Networks, Vol. 1, pp. 275–276.

    Article  Google Scholar 

  18. Linares-Barranco, B., Sanchez-Sinencio, E., Rodriguez-Vazquez, A., and Huertas, J.L. (1992), “A modular T-mode design approach for analog neural network hardware implementations, ” IEEE Journal of Solid-State Circuits, Vol. 27, no. 5, pp. 701–713.

    Article  Google Scholar 

  19. Ho, C.S., Liou, JJ., Georgiopoulos, M., Heileman, G.L., and Christodoulo, C. (1994), “Analogue circuit design and implemen­tation of an adaptive resonance theory (ART) neural network ar­chitecture, ” International Journal of Electronics, Vol. 76, no. 2, pp. 271–291.

    Article  Google Scholar 

  20. Tsay, S.W. and Newcomb, R.W. (1991), “VLSI implementation of ART1 memories, ” IEEE Transactions on Neural Networks, Vol. 2, pp. 214–221, March.

    Article  Google Scholar 

  21. Wunsch II, D.C., Caudell, T.P., Capps, CD., Marks II, R.J., and Falk, R.A. (1993), “An optoelectronic implementation of the adaptive resonance neural network, ” IEEE Transactions on Neural Networks, Vol. 4, no. 4, pp. 673–684, July.

    Article  Google Scholar 

  22. Serrano-Gotarredona, T. and Linares-Barranco, B. (1996), “A modified ART1 algorithm more suitable for VLSI implementations, ” Neural Networks, Vol. 9, no. 6, pp. 1025–1043.

    Article  Google Scholar 

  23. Serrano-Gotarredona, T. and Linares-Barranco, B. (1996), “A realtime clustering microchip neural engine, ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, no. 2, pp. 195–209.

    Article  Google Scholar 

  24. Lazzaro, J., Ryckebush, R., Mahowald, M.A., and Mead, C (1989), “Winner-take-all networks of O(n) complexity, ” in Advances in Neural Information Processing Systems, Touretzky, D.S. Ed., Vol. 1, pp. 703–711. Morgan-Kaufmann, Los Altos, CA.

    Google Scholar 

  25. Rodriguez-Vazquez, A., Dominguez-Castro, R., Medeiro, R, and Delgado-Resti-tuto, M. (1995), “High resolution CMOS current comparators: Design and application to current-mode function generation,” International Journal of Analog Integrated Circuits and Signal Processing, Vol. 7, pp. 149–165.

    Article  Google Scholar 

  26. Mead, C. (1989), Analog VLSI and Neural Systems, Addison Wesley, Reading, MA.

    Book  MATH  Google Scholar 

  27. Serrano-Gotarredona, T. and Linares-Barranco, B. (1994), “The active-input regulated-cascode current mirror, ” IEEE Transactionson Circuits and Systems, Parti: Fundamental Theory and Applications, Vol. 41, no. 6, pp. 464–467.

    Article  Google Scholar 

  28. Serrano-Gotarredona, T. and Linares-Barranco, B. (1995), “A modular current-mode high-precision winner-take-all circuit,” IEEETransactions on Circuits and Systems, Part II, Vol. 42, no. 2, pp. 132–134.

    Article  Google Scholar 

  29. Serrano-Gotarredona, T. and Linares-Barranco, B. (1998), “A high-precision current-mode WTA-MAX circuit with multi-chip capability,” IEEE Journal of Solid-State Circuits, Vol. 33, no. 2, pp. 280–286.

    Article  Google Scholar 

  30. Pelgrom, M.J.M., Duinmaijer, A.C.J., and Welbers, A.P.G. (1989), “Matching properties of MOS transistors,” IEEE Journal ofSolid-State Circuits, Vol. 24, pp. 1433–1440.

    Article  Google Scholar 

  31. Serrano-Gotarredona, T. and Linares-Barranco, B. (1999), “Sys­tematic width-and-length dependent cmos transistor mismatch characterization and simulation,” International Journal of Analog Integrated Circuits and Signal Processing.

    Google Scholar 

  32. Gregor, R.W. (1992), “On the relationship between topography and transistor matching in an analog CMOS technology,” IEEE Transactions on Electron Devices, Vol. 39, no. 2, pp. 275–282.

    Article  Google Scholar 

  33. Lakshmikumar, K.R., Hadaway, R.A., and Copeland, M.A. (1986), “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE Journal of Solid-State Circuits, Vol. SC-21, no. 6, pp. 1057–1066.

    Article  Google Scholar 

  34. Michael, C. and Ismail, M. (1992), “Statistical modeling of device mismatch for analog MOS integrated circuits,” IEEE Journal of Solid-State Circuits, Vol. 27, no. 2, pp. 154–166.

    Article  Google Scholar 

  35. Shyu, J.B., Temes, G.C., and Krummenacher, F. (1984), “Random error effects in matched MOS capacitors and current sources,” IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 6, pp. 948–955.

    Article  Google Scholar 

  36. Allen, RE. and Holberg, D.R. (1987), CMOS Analog Design, Holt Rinehart and Winston Inc., New York.

    Google Scholar 

  37. Strader, N.R. and Harden, J.C. (1989), “Architectural yield optimization,” in Wafer Scale Integration, Schwartzlander, E.E. Ed., pp. 57–118. Kluwer Academic Publishers, Boston.

    Chapter  Google Scholar 

  38. Chu, L.C. (1991), “Fault-tolerant model of neural computing,” IEEE Int. Conf on Computer Design: VLSI in Computers and Pro-cessors, pp. 122–125.

    Google Scholar 

  39. Neti, C, Schneider, M.H., and Young, E.D. (1992), “Maximally fault tolerant neural networks,” IEEE Transactions on Neural Networks, Vol. 3, no. 1, pp. 14–23.

    Article  Google Scholar 

  40. Kim, J.H., Lursinsap, C, and Park, S. (1991), “Fault-tolerant ar­tificial neural networks,” Int. Joint Conf. on Neural Networks (IJCNNy 91), Vol. 2, pp. 951.

    Article  Google Scholar 

  41. Serrano-Gotarredona, T. and Linares-Barranco, B. (1997), “An ART1 microchip and its use in multi-ARTl systems,” IEEE Trans­actions on Neural Networks, Vol. 8, no. 5, pp. 1184–1194.

    Article  Google Scholar 

  42. Carpenter, G.A., Grossberg, S., and Reynolds, J.H. (1991), “ARTMAP: Supervised real-time learning and classification of nonstationary data by a self-organizing neural network,” NeuralNetworks, Vol. 4, pp. 759–771.

    Google Scholar 

  43. Medeiro, E, Rodriguez-Macias, R., Fernandez, F.V., Domfnguez-Castro, R., and Rodriguez-Vazquez, A. (1994), “Global analogue cell design and optimization using statistical techniques,” Analog Integrated Circuits and Signal Processing, Vol. 6, pp. 179–195.

    Article  Google Scholar 

  44. Bastos, J., Steyaert, M., Roovers, R., Kinger, P., Sansen, W., Graindourze, B., Pergoot, A., and Janssens, E. (1995), “Mismatch char­acterization of small size MOS transistors” Proc. IEEE 1995 Int. Conf. Microelectronic Test Structures, Vol. 8, pp. 271–276.

    Google Scholar 

  45. Bastos, J., Steyaert, M., Pergoot, A., and Sansen, W. (1997), “Mismatch characterization of submicron MOS transistors,” Analog Integrated Circuits and Signal Processing, Vol. 12, pp. 95–106.

    Article  Google Scholar 

  46. Rade, L. and Westergren, B. (1990), BETA Mathematics Handbook, CRC Press.

    MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. National Microelectronics Center, Sevilla, Spain

    T. Serrano-Gotarredona & B. Linares-Barranco

Authors
  1. T. Serrano-Gotarredona
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. B. Linares-Barranco
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Knowledge-Based Intelligent Engineering Systems Centre, University of South Australia, Adelaide, Mawson Lakes, South Australia, 5095

    Lakhmi C. Jain

  2. Dipartimento di Ingegneria della Informazione, University of Pisa, Via Diotisalvi, 2, 56126, Pisa, Italy

    Beatrice Lazzerini

  3. Department of Electrical Engineering, Middle East Technical University, 06531, Ankara, Turkey

    Ugur Halici

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Serrano-Gotarredona, T., Linares-Barranco, B. (2000). Adaptive Resonance Theory Microchips. In: Jain, L.C., Lazzerini, B., Halici, U. (eds) Innovations in ART Neural Networks. Studies in Fuzziness and Soft Computing, vol 43. Physica, Heidelberg. https://doi.org/10.1007/978-3-7908-1857-4_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-7908-1857-4_8

  • Publisher Name: Physica, Heidelberg

  • Print ISBN: 978-3-7908-2469-8

  • Online ISBN: 978-3-7908-1857-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation