High Performance Fuzzy Processors
In this chapter, some methodologies for developing fuzzy hardware architectures are presented. The architectures can be grouped into two sets, namely general-purpose structures, and task oriented structures. We discuss the effectiveness of the task-oriented architectures for the implementation of fuzzy processors. We present an architecture exploiting the properties of the fuzzy processing in order to simplify and speed-up its basic blocks. In particular, the fuzzification unit is based on a suitable class of trapezoidal membership functions with power of two slopes for the oblique sides. The algorithm used for the defuzzification unit is based on the Center of Gravity (COG) method. It is implemented by a full look-up table approach in order to obtain the maximum speed. With respect to other look-up table approaches the architecture we propose uses less memory and is fully parallel. In addition, a divider that computes an approximate result has been added and further reduces the overall complexity of the circuit. The structure has been designed and simulated by using the ES2 technology. We obtained a chip of 7 mm2 for the core logic, and an external 10 Kbytes memory containing the output membership functions. The simulations have shown a speed over 100 KFLIPS for 2 inputs and 20 rules. The effectiveness of this architecture has been tested on a specific high-speed application, i.e. the radar target tracking. In this case, the simulation results give good performance in terms of target tracking capability and speed higher than 400 KFLIPS.
KeywordsMembership Function Fuzzy Logic Hardware Implementation Lookup Table Fuzzy Logic Controller
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