High Performance Fuzzy Processors

  • Gian Carlo Cardarilli
  • Roberto Lojacono
  • Marco Re
Part of the Studies in Fuzziness and Soft Computing book series (STUDFUZZ, volume 74)


In this chapter, some methodologies for developing fuzzy hardware architectures are presented. The architectures can be grouped into two sets, namely general-purpose structures, and task oriented structures. We discuss the effectiveness of the task-oriented architectures for the implementation of fuzzy processors. We present an architecture exploiting the properties of the fuzzy processing in order to simplify and speed-up its basic blocks. In particular, the fuzzification unit is based on a suitable class of trapezoidal membership functions with power of two slopes for the oblique sides. The algorithm used for the defuzzification unit is based on the Center of Gravity (COG) method. It is implemented by a full look-up table approach in order to obtain the maximum speed. With respect to other look-up table approaches the architecture we propose uses less memory and is fully parallel. In addition, a divider that computes an approximate result has been added and further reduces the overall complexity of the circuit. The structure has been designed and simulated by using the ES2 technology. We obtained a chip of 7 mm2 for the core logic, and an external 10 Kbytes memory containing the output membership functions. The simulations have shown a speed over 100 KFLIPS for 2 inputs and 20 rules. The effectiveness of this architecture has been tested on a specific high-speed application, i.e. the radar target tracking. In this case, the simulation results give good performance in terms of target tracking capability and speed higher than 400 KFLIPS.


Membership Function Fuzzy Logic Hardware Implementation Lookup Table Fuzzy Logic Controller 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    Watanabe H., Dettloff W.D., and Yount K.E., “A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture,” IEEE J. on Solid State Circuits, vol. 25, no. 2, pp. 376–382, 1990.CrossRefGoogle Scholar
  2. [2]
    Chiueh T., “Optimization of Fuzzy Logic Inference Architecture”, IEEE Computer, pp. 67–71, 1992.Google Scholar
  3. [3]
    Eichfeld H., Lohner M., and Muller M., “Architecture of a CMOS Fuzzy Logic Controller with Optimized Memory Organization and Operator Design”, Proc. IEEE Int. Conf. Fuzzy System, San Diego, CA, pp. 13171323, 1992.Google Scholar
  4. [4]
    Nakamura K., Sakascita N., Nitta Y., Shimoumura K., and Tokuda T., “Fuzzy Inference and Fuzzy Inference Processor”, IEEE Micro, pp. 37–48, 1993.Google Scholar
  5. [5]
    Eichfeld H., Klimke M., Nolles J., and Kunemund T., “A General-Purpose Inference Processor”, Proc. of Fourth Int. Conf. on Microlectronics for Neural Networks and Fuzzy Logic, Turin, Italy, September 26–28, 1994.Google Scholar
  6. [6]
    Eisele M., Hentschel K., and Kunemund T., “Hardware Realization of Fast Defuzzification by Adaptive Integration”, Proc. Fourth Int. Conf. on Microlectronics for Neural Networks and Fuzzy Logic, Turin, Italy, September 26–28, 1994.Google Scholar
  7. [7]
    Colodro F., Torralba A., and Franquelo L.G., “A Digital Fuzzy-Logic Controller with a Simple Architecture”, Proc. Intern. Conf. Circuits and Systems, London, U.K., Vol. 2, pp. 101, 1994.Google Scholar
  8. [8]
    Cardarilli G.C., Re M., and Salerno M., “Multiplierless Digital Architecture for Membership Function Evaluation”, Proc. Int. Conf. on Neural Information Processing, Seoul, Korea, October 17–20, 1994.Google Scholar
  9. [9]
    D. Park, and E.W. Kang, “Radar Target Tracking with a Fuzzy Filter”, ICONIP 1994 Proc. Int. Conf. on Neural Information Processing, Seoul, Korea, 17–20 October, 1994.Google Scholar
  10. [10]
    Costa A., De Gloria A., Faraboschi P., Pagni A., and Rizzotto G., “Hardware Solutions for Fuzzy Control”, Proc. of IEEE, vol. 83, no. 3, pp. 422–434, 1995CrossRefGoogle Scholar
  11. [11]
    Cardarilli G.C., Lojacono R., Re M., and Salerno M., “A VLSI Defuzzification Architecture for Real Time Fuzzy Processor”, Proc. Third European Congress on Intelligent Techniques and Soft Computing, Aachen, Germany, August 28–31, 1995.Google Scholar
  12. [12]
    Eichfeld H., Kunemund T., and Menke M., “A 12b General-Purpose Fuzzy Logic Controller Chip”, IEEE Trans. on Fuzzy Systems, vol. 4, no. 4, pp. 460–475, 1996.CrossRefGoogle Scholar
  13. [13]
    Patyra M.J., Grantner J.L., and Koster K., “Digital Fuzzy Logic Controller: Design and Implementation”, IEEE Trans. on Fuzzy Systems, vol. 4, no. 4, pp. 439–459, 1996.CrossRefGoogle Scholar
  14. [14]
    Cardarilli G.C., Lojacono R., Re M., and Carfagnini L., “High Speed Fuzzy Filter for Non-Linear Channel Equalizing”, Proc. Int. Symposium on Fuzzy Logic, Zurich, Switzerland, February 13–14, 1997.Google Scholar
  15. [15]
    Cardarilli G.C., Lojacono R., and Re M., “VLSI Implementation of a Real Time Fuzzy Processor”, J. of Intelligent and Fuzzy Systems, IOS Press, n. 6, pp. 389–401, 1998.Google Scholar
  16. [16]
    ST52T301/E301, Advanced Data Sheet,“ STMicroelectronics, 1998Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Gian Carlo Cardarilli
    • 1
  • Roberto Lojacono
    • 1
  • Marco Re
    • 1
  1. 1.Departament of ElectronicsUniversity of Rome “Tor vergata”RomeItaly

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