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Automated Design Synthesis and Partitioning for Adaptive Reconfigurable Hardware

  • Ranga Vemuri
  • Sriram Govindarajan
  • Iyad Ouaiss
  • Meenakshi Kaul
  • Vinoo Srinivasan
  • Shankar Radhakrishnan
  • Sujatha Sundaraman
  • Satish Ganesan
  • Awartika Pandey
  • Preetham Lakshmikanthan
Part of the Studies in Fuzziness and Soft Computing book series (STUDFUZZ, volume 74)

Abstract

The advent of reconfigurable logic arrays facilitates the development of adaptive architectures that have wide applicability as stand-alone intelligent systems. The hardware structure of such architectures can be rapidly altered to suit the changing computational needs of an application during its execution. The power of adaptive architectures has been demonstrated primarily in image processing, digital signal processing, and other areas such as neural networks and genetic algorithms. This chapter discusses the state-of-the-art adaptive architectures, their classification, and their applications.

Keywords

Field Programmable Gate Array Memory Bank Design Space Exploration Data Flow Graph Spatial Partitioning 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Ranga Vemuri
    • 1
  • Sriram Govindarajan
    • 1
  • Iyad Ouaiss
    • 1
  • Meenakshi Kaul
    • 1
  • Vinoo Srinivasan
    • 1
  • Shankar Radhakrishnan
    • 1
  • Sujatha Sundaraman
    • 1
  • Satish Ganesan
    • 1
  • Awartika Pandey
    • 1
  • Preetham Lakshmikanthan
    • 1
  1. 1.Digital Design Environments Laboratory, ECECS Department, ML 0030University of CincinnatiCincinnatiUSA

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