Advertisement

Algebras for Hazard Detection

  • Janusz Brzozowski
  • Zoltán Ésik
  • Yaacov Iland
Part of the Studies in Fuzziness and Soft Computing book series (STUDFUZZ, volume 114)

Abstract

Hazards pulses are undesirable short pulses caused by stray delays in digital circuits. Such pulses not only may cause errors in the circuit operation, but also consume energy, and add to the computation time. It is therefore very important to detect hazards in circuit designs. Two-valued Boolean algebra, which is commonly used for the analysis and synthesis of digital circuits, cannot detect hazard conditions directly. To overcome this limitation several multi-valued algebras have been proposed for hazard detection. This paper surveys these algebras, and studies their mathematical properties. Also, some recent results unifying most of the multi-valued algebras presented in the literature are described. Our attention in this paper is restricted to the study of static and dynamic hazards in gate circuits.

Keywords

Partial Order Boolean Algebra Relay Network Switching Circuit Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Andrew, R.: An Algorithm for Eight-Valued Simulation and Hazard Detection in Gate Networks. Proc. 16th Int. Symp. on Multiple-Valued Logic, IEEE (1986) 273–280Google Scholar
  2. 2.
    Balbes, R.: Free Ternary Algebras. Int. J. Algebra and Computation, vol. 10, no. 6 (2000) 739–749MathSciNetMATHCrossRefGoogle Scholar
  3. 3.
    Beare, B.D. and Brzozowski, J.A.: An Exploration of the Properties of a Thirteen-Valued Algebra. Unpublished (1999)Google Scholar
  4. 4.
    Breuer, M.A. and Friedman, A.D.: Diagnosis and Reliable Design of Digital Systems. Computer Science Press (1976)Google Scholar
  5. 5.
    Breuer, M.A. and Harrison, R.L.: Procedures for Eliminating Static and Dynamic Hazards in Test Generation. IEEE Trans. Comput., vol. C-23, no. 10, (1974) 1069–1078CrossRefGoogle Scholar
  6. 6.
    Brzozowski, J.A.: De Morgan Bisemilattices. Int. Symp. on Multiple-Valued Logic. IEEE (2000) 173–178Google Scholar
  7. 7.
    Brzozowski, J.A.: A Characterization of de Morgan Algebras. Int. Journal of Algebra and Computation. Vol. 11, No. 5, (2001) 525–527MathSciNetMATHCrossRefGoogle Scholar
  8. 8.
    Brzozowski, J.A. and Ésik, Z.: Hazard Algebras (Extended Abstract). A Half-Century of Automata Theory, Salomaa, A., Wood, D. and Yu, S. eds., World Scientific, Singapore (2001) 1–19CrossRefGoogle Scholar
  9. 9.
    Brzozowski, J.A. and Ésik, Z.: Hazard Algebras, Maveric Report 00–2, University of Waterloo, Waterloo, ON, Canada, 27 pp., July (2000); revised December (2001). http://maveric.uwaterloo.ca/publication.html Google Scholar
  10. 10.
    Brzozowski, J.A., Lou, J.J. and Negulescu, R.: A Characterization of Finite Ternary Algebras. Int. J. Algebra and Computation, vol. 7, no. 6 (1997) 713–721MathSciNetMATHCrossRefGoogle Scholar
  11. 11.
    Brzozowski, J.A. and Seger, C-J.: Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks. Proc. Coll. Automata, Languages and Programming, Kott, L. ed., Springer-Verlag, Berlin, July (1986) 69–78Google Scholar
  12. 12.
    Brzozowski, J.A. and Seger, C-J.: A Characterization of Ternary Simulation of Gate Networks. IEEE Trans. Computers, vol. C-36, no. 11, November (1987), 1318–1327Google Scholar
  13. 13.
    Brzozowski, J.A. and Seger, C-J.: Asynchronous Circuits, Springer-Verlag, Berlin (1995)CrossRefGoogle Scholar
  14. 14.
    Chakraborty, T., Agrawal, V. and Bushnell, M.: Delay Fault Models and Test Generation for Random Logic Sequential Circuits. Proc. Design Automation Conf., IEEE, June (1992) 165–172Google Scholar
  15. 15.
    Chakraborty, S. and Dill, D.L.: More Accurate Polynomial-Time Min-Max Timing Simulation. Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, April (1997) 112–123Google Scholar
  16. 16.
    Chakraborty, S., Dill, D.L. and Yun, K.Y.: Min-Max Timing Analysis and An Application to Asynchronous Circuits. Proc. IEEE (1999) 1–13Google Scholar
  17. 17.
    Eichelberger, E.B.: Hazard Detection in Combinational and Sequential Switching Circuits. IBM J. Res. and Dev., vol. 9, (1965) 90–99MATHGoogle Scholar
  18. 18.
    Ésik, Z.: A Cayley Theorem for Ternary Algebras. Int. J. Algebra and Computation, vol. 8, no. 3, (1998) 311–316MathSciNetMATHCrossRefGoogle Scholar
  19. 19.
    Ésik, Z.: Free De Morgan bisemigroups and bisemilattices. Algebra Colloquium, to appearGoogle Scholar
  20. 20.
    Fantauzzi, G.: An Algebraic Model for the Analysis of Logical Circuits. IEEE Trans. Computers, vol. C-23, no. 6, (1974) 576–581CrossRefGoogle Scholar
  21. 21.
    Gheorghiu, M.: Circuit Simulation Using a Hazard Algebra. MMath Thesis, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1, December (2001) http://maveric.uwaterloo.ca/publication.html Google Scholar
  22. 22.
    Goto, M.: Application of Three-Valued Logic to Construct the Theory of Relay Networks (in Japanese). Proc. Joint Meeting IEE, IECE, and I. of Ilium. E. of Japan, (1948)Google Scholar
  23. 23.
    Goto, M.: Application of Logical Mathematics to the Theory of Relay Networks (in Japanese). J. Inst. Elec. Eng of Japan, vol. 69, no. 729, (1949)Google Scholar
  24. 24.
    Grätzer, G.: Universal Algebra. Second Edition, Springer-Verlag (1979)MATHGoogle Scholar
  25. 25.
    Hayes, J.P.: Digital Simulation with Multiple Logic Values. IEEE Trans. CAD, vol. CAD-5, no. 2 (1986) 274–283Google Scholar
  26. 26.
    Hlawiczka, A. and Badura, D.: The Method of Recognition of Critical Hazards, Critical Races, Essential Hazards and D-Trio. Proc. Int. Symp. Multiple-Valued Logic, IEEE, (1982) 298–311Google Scholar
  27. 27.
    Huffman, D.A.: The Design and Use of Hazard-Free Switching Circuits. J. ACM, vol. 4 (1957) 47–62MathSciNetCrossRefGoogle Scholar
  28. 28.
    Keister, W., Ritchie, A.E. and Washburn, S.H.: The Design of Switching Circuits. D. Van Nostrand, New York (1951)Google Scholar
  29. 29.
    Knudsen, M.S.: A Compact Nine-Valued Logic Simulation Algorithm. Proc. Int. Symp. Circuits and Systems, vol. 3, IEEE, (1982) 1190–1193Google Scholar
  30. 30.
    Knudsen, M.S.: A Nine-Valued Logic Simulator for Digital N-MOS Circuits. Proc. Int. Symp. Multiple-Valued Logic. IEEE, (1982) 293–297Google Scholar
  31. 31.
    Kung, D.S.: Hazard-Non-Increasing Gate-Level Optimization Algorithms. Proc. Int. Conf. Computer-Aided Design, IEEE, (1992) 631–634Google Scholar
  32. 32.
    Lewis, D.W.: Hazard Detection by a Quinary Simulation of Logic Devices with Bounded Propagation Delays, MSc Thesis, University of Syracuse (1972)Google Scholar
  33. 33.
    McCluskey, E.J.: Transient Behavior of Combinational Logic Circuits. In Redundancy Techniques for Computing Systems. Wilcox, R.H. and Mann, W.C. eds., Spartan Books, Washington, DC (1962) 9–46Google Scholar
  34. 34.
    Metze, G.A.: Many-Valued Logic and the Design of Switching Circuits, MSc Thesis, University of Illinois, Urbana (1953)Google Scholar
  35. 35.
    Moisil, Gr.C.: Sur l’application des logiques it trois valeurs à l’étude des schémas à contacts et relais. Actes proc. congr. intern. automatique, (1956) 48Google Scholar
  36. 36.
    Muller, D.E.: Treatment of Transition Signals in Electronic Switching Circuits by Algebraic Methods. IRE Trans. Electronic Computers, vol. EC-8, no. 3, (1959) 401Google Scholar
  37. 37.
    Muth, P.: A Nine-Valued Circuit Model for Test Generation. IEEE Trans. Computers, vol. C-25, no. 6, (1976)Google Scholar
  38. 38.
    Roginskii, V.N.: The Operation of Relay Networks in Transitional Periods. Avtomatika i Telemekhanika, vol. 20, no. 10, (1959) 1408–1416Google Scholar
  39. 39.
    Seger, C-J. and Brzozowski, J.A.: Generalized Ternary Simulation of Sequential Circuits. Theoretical Informatics and Applications, vol. 28, No. 3–4, (1994) 159–186MATHGoogle Scholar
  40. 40.
    Shannon, C.E.: A Symbolic Analysis of Relay and Switching Circuits. Trans. AIEE, vol. 57 (1938) 713–723Google Scholar
  41. 41.
    Thompson, E.W. and Szygenda, S.A.: Three Levels of Accuracy for the Simulation of Different Fault Types in Digital Systems. Proc. Design Automation Conference, IEEE (1975) 105–113Google Scholar
  42. 42.
    Unger, S.H.: Asynchronous Sequential Switching Circuits. Wiley-Interscience, New York (1969)Google Scholar
  43. 43.
    Yoeli, M. and Rinon, S.: Application of Ternary Algebra to the Study of Static Hazards. J. ACM, vol. 11, no. 1, (1964) 84–97MATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Janusz Brzozowski
    • 1
  • Zoltán Ésik
    • 2
  • Yaacov Iland
    • 1
  1. 1.School of Computer ScienceUniversity of WaterlooWaterlooCanada
  2. 2.Department of Computer ScienceUniversity of SzegedSzegedHungary

Personalised recommendations