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The MASTER Framework

  • P. J. Hopper
  • P. A. Blakey

Abstract

The MASTER Framework has a two level architecture. The first level consists of a standard structure format and a set of ’MASTER Tools’. This provides a high quality utility based framework that supports highly interactive use. The second level is a ’Virtual Wafer Fab’ that adds capabilities for large-scale simulation-based design and experimentation. Powerful semiconductor technology CAD systems are constructed by populating The MASTER Framework with conforming process and device simulators.

Keywords

Device Simulation Multiple Simulator Misalignment Tolerance Selected Input Parameter Simulator Library 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag/Wien 1993

Authors and Affiliations

  • P. J. Hopper
    • 1
  • P. A. Blakey
    • 1
  1. 1.Silvaco InternationalSanta ClaraUSA

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