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Modeling Hot-Carrier Effects

  • Narain Arora
Part of the Computational Microelectronics book series (COMPUTATIONAL)

Abstract

Over the past decade, the downward scaling of device dimensions has resulted in a reduction in gate-oxide thickness by a factor of four. While scaling continued, the supply voltage remained constant (normally 5 V) due to the constraints of retaining compatibility with existing systems. This has resulted in increased vertical electric fields in the oxide which have already reached above 1 MV/cm in thin oxides. The scaling of channel length, meanwhile, has lead to large lateral electric field in the channel. In spite of reducing the supply voltage to 3.3 V, a strong push still remains towards higher channel electric field as scaling continues. The increased channel electric field has caused hot-carrier effects that are becoming a limiting factor in realizing submicron level VLSI. This is because hot-carrier effects impose more severe constraints on VLSI device design as device dimensions are reduced.

Keywords

Gate Voltage Gate Oxide Substrate Current Gate Current Device Degradation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag/Wien 1993

Authors and Affiliations

  • Narain Arora
    • 1
  1. 1.Digital Equipment CorporationHudsonUSA

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