MOS Transistor Structure and Operation

  • Narain Arora
Part of the Computational Microelectronics book series (COMPUTATIONAL)


In this chapter we will give an overview of the MOS transistor as used in VLSI technology, and its behavior under operating biases will be explained qualitatively. First we will describe the basic MOSFET structure and then qualitatively discuss its current-voltage characteristics. During the last two decades, device lengths have been reduced from 20 μm to less than a micron, which has resulted in high fields in the device. The rules of device scaling are first discussed followed by the impact of high field effects on device characteristics. Although there are various high field effects, the one which is of most concern for VLSI design is the so called hot-carrier effects. Only an overview is covered in this chapter, the detailed hot-carrier modeling is the subject of discussion in Chapter 8. Finally, a brief description of device structures specifically for VLSI design, that is important from a device modeling point of view, will be covered.


Gate Voltage Gate Oxide Junction Depth Drain Region Polysilicon Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    C. T. Sah, ‘Characteristics of the metal-oxide-semiconductor transistors’,IEEE Trans. Electron Devices, ED-11, pp. 324–345 (1964).CrossRefGoogle Scholar
  2. [2]
    P. Richman, MOS Field-Effect Transistors and Integrated Circuits ,John Wiley &Sons, New York, 1973.Google Scholar
  3. [3]
    Y. P. Tsividis, Operation and Modeling of the MOS Transistor ,McGraw-Hill Book Company, New York, 1987.Google Scholar
  4. [4]
    F. C. Hsu, P. K. Ko, S. Tam, C. Hu, and R. S. Muller, ‘An analytical breakdown model for short-channel MOSFETs’,IEEE Trans. Electron Devices, ED-29, pp. 1735–1740 (1982).Google Scholar
  5. [5]
    F. C. Hsu, R. S. Muller, and C. Hu, ‘A simplified model of short-channel MOSFET characteristics in the breakdown mode’,IEEE Trans. Electron Devices, ED-30, pp. 571–576 (1983).Google Scholar
  6. [6]
    M. Pinto-Guedes and P. C. Chan, ‘A circuit model for bipolar-induced breakdown in MOSFET’L419, IEEE Trans. Compter-Aided Design, CAD-7, pp. 289–294 (1988).CrossRefGoogle Scholar
  7. [7]
    S. Vaidya, E. N. Fuls, and R. L. Johnston, ‘NMOS ring oscillators with cobalt-silicided-diffused shallow junctions formed during poly-plug contact doping cycle’,IEEE Trans. Electron Devices, ED-33, pp. 1321–1328 (1986).CrossRefGoogle Scholar
  8. [8]
    R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, ‘Design of ion-implanted MOSFETs with very small physical dimensions’,IEEE J. Solid-State Circuits, SC-9, pp. 256–268 (1974).CrossRefGoogle Scholar
  9. [9]
    J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, ‘Generalized guide for MOSFET miniaturization’,IEEE Electron Devices Lett., EDL-1, pp. 2–5 (1980).CrossRefGoogle Scholar
  10. [10]
    J. W. Mathews and C. K. Erdelyi, ‘Power supply voltages for future VLSI’,IEEE Proc. CICC, pp. 149–152 (1986).Google Scholar
  11. [11]
    M. Kakumu, M. Kinugawa, K. Hashimoto, and J. Matsunaga, ‘Power supply voltage for future CMOS VLSI in half and sum-micrometer’,IEEE IEDM-86, Tech. Dig., pp. 399–402 (1986).Google Scholar
  12. [12]
    P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, ‘The impact of scaling laws on the choice of n-channel and p-channel for MOS VLSI’,IEEE Trans. Electron Device Lett., EDL-1, pp. 220–223 (1980).CrossRefGoogle Scholar
  13. [13]
    H. Shichijo, ‘A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI’,Solid-State Electron., 26, pp. 969–986 (1983).CrossRefGoogle Scholar
  14. [14]
    G. Baccarani, M. R. Wordeman, and R. H. Dennard, ‘Generalized scaling theory and its application to 1/4 micron MOSFET design’,IEEE Trans. Electron Devices, ED-31, pp. 452–462 (1984).CrossRefGoogle Scholar
  15. [15]
    N. G. Einspruch and G. Gildenblat, Eds., Advanced MOS Device Physics ,VLSI Electronics Vol. 18, Academic Press Inc., New York, 1989.Google Scholar
  16. [16]
    Y. W. Sing and B. Sudlow, ‘Modeling and VLSI design constraints of substrate current’,IEEE IEDM-80, Dig. Tech. Papers ,pp. 732–735 (1980).Google Scholar
  17. [17]
    B. Eitan, D. Frohman-Bentchkowsky, and J. Shappir, ‘Holding time degradation in dynamic MOS RAM by injection-induced electron currents’,IEEE Trans. Electron Devices, ED-28, pp. 1515–1519 (1981).CrossRefGoogle Scholar
  18. [18]
    E. Takeda, A. Shimizu, and T. Hagiwara, ‘Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFETs’,IEEE Electron Device Lett., EDL-4, pp. 329–331 (1983).CrossRefGoogle Scholar
  19. [19]
    E. Takeda, H. Kume, T. Toyabe, and S. Asai, ‘A submicrometer MOSFET structure for minimizing hot-carrier generation’,IEEE Trans. Electron Devices, ED-29, pp. 611–618 (1982).CrossRefGoogle Scholar
  20. [20]
    E. Takeda, ‘Hot-carrier effects in submicrometer MOS VLSI’,Proc. IEE, 131, Pt I, no. 5, pp. 153–164(1984).MathSciNetGoogle Scholar
  21. [21]
    J. J. Sanchez, K. K. Hsueh, and T. A. DeMassa, ‘Drain-engineered hot-electron-resistant device structures-A Review’,IEEE Trans. Electron Devices, ED-36, pp. 1125–1131 (1989).CrossRefGoogle Scholar
  22. [22]
    D. Frohman-Bentchkowsky, ‘FAMOS-A new semiconductor charge storage device’, Solid-State Electron., 17, pp. 517–529 (1974).CrossRefGoogle Scholar
  23. [23]
    K. M. Cham, S. Y. Oh, D. Chin, J. L. Moll, K. Lee, and P. V. Voorde, Computer-Aided Design and VLSI Device Development ,2nd Ed., Kluwer Academic Publisher, Boston, 1988.CrossRefGoogle Scholar
  24. [24]
    J. M. Pimbley, M. Ghezzo, H. G. Parks, and D. M. Brown, in: Advanced CMOS Process Technology (N. G. Einspruch, Ed.), VLSI Electronics: Microstructure Science, Vol. 19, Academic Press Inc., New York, 1989.Google Scholar
  25. [25]
    J. Y. Chen, ‘CMOS Devices and Technology for VLSV’ ,Prentice Hall, Englewood Cliffs, NJ, 1990.Google Scholar
  26. [26]
    S. P. Murarka, Silicide for VLSI Applications ,Academic Press, New York, 1983.Google Scholar
  27. [27]
    D. L. Kwong, Y. H. Ku, S. K. Lee, E. Louis, N. J. Alvi, and P. Chu, ‘Silicided shallow junction formation by ion implantation of impurity ions into silicide layers and subsequent drivein’, J. Appl. Phys., 61, pp. 5084–5088 (1987).CrossRefGoogle Scholar
  28. [28]
    L. Van den Hove, R. Wolters, K. Maer, R. F. De Keersmaecker, and G. J. Declerack, ‘A self-sligned CoSiO2 interconnection and contact technology for VLSI applications’, IEEE Trans. Electron Devices, ED-34, pp. 554–562 (1987).CrossRefGoogle Scholar
  29. [29]
    C. Y. Wong, J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, ‘Doping of N+ and P+ poly-Si in a dual-gate CMOS process’, IEEE-IEDM88, Tech. Dig., pp. 238–241 (1988).Google Scholar
  30. [30]
    M. Koyanagi, H. Kaneko, and S. Shinizu, ‘Optimum design of n + -n- double-diffused drain MOSFETS to reduce hot-carrier emission’, IEEE Trans. Electron Devices, ED-32, pp. 562–570 (1985).CrossRefGoogle Scholar
  31. [31]
    S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, ‘Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor’, IEEE Trans. Electron Devices, ED-27, pp. 1359–1367 (1980).CrossRefGoogle Scholar
  32. [32]
    P. J. Tsang, S. Ogura, W. W. Walker, J. F. Shepard, and D. L. Critchlow, ‘Fabrication of high-performance LDD FETS with sidewall spacer technology’, IEEE Trans. Electron Devices, ED-29, pp. 590–596 (1982).CrossRefGoogle Scholar
  33. [33]
    R. D. Rug, H. Momose, and Y. Nagakubo, ‘Deep trench isolated CMOS devices’, IEEE-IEDM82, Tech. Dig. ,p. 62– (1982)Google Scholar
  34. [33]
    R. D. Rung, ‘Trench isolation prospects for application in CMOS VLSI’, IEEE-IEDM84, Tech. Dig. ,p. 574–578 (1984)Google Scholar
  35. [34]
    R. R. Troutman, Latchup in CMOS Technology: The Problem and Its Cure ,Kluwer Academic Publisher ,Boston ,1987.Google Scholar
  36. [35]
    K. K. Ng and W. T. Lynch ,The impact of intrinsic series resistance as MOSFET scaling‘ ,IEEE Trans. Electron Devices’ ,ED-34 ,pp. 503–511 (1987).CrossRefGoogle Scholar
  37. [36]
    G. Sh. Gildenblat and S. S. Cohen ,‘Contact metalization’ ,in: N. G. Einspruch and G. Gildenblat ,Eds., VLSI Electronics Vol. 15 ,Academic Press Inc., New York ,1987.Google Scholar
  38. [37]
    J. M. Pimbley ,E. Cumberbatch ,and P. S. Hagan ,‘Analytical treatment of MOSFET source-drain resistance’ ,IEEE Trans. Electron Devices ,ED-34 ,pp. 834–838 (1987).CrossRefGoogle Scholar
  39. [38]
    G. Baccarani and G. A. Sai-Halasz ,‘Spreading resistance in submicron MOSFETs’ IEEE Trans. Electron Device Lett., EDL-4 ,pp. 27–29 (1983).CrossRefGoogle Scholar
  40. [39]
    K. K. Ng and W. T. Lynch ,‘Analysis of the gate-voltage dependent series resistance of MOSFETs’ ,IEEE Trans. Electron Devices ,ED-33 ,pp. 965–972 (1986).CrossRefGoogle Scholar
  41. [40]
    J. M. Pimbley ,‘Two dimensional current flow in the MOSFET source-drain’ ,IEEE Trans. Electron Devices ,ED-33 ,pp. 986–996 (1986).CrossRefGoogle Scholar
  42. [41]
    W. M. Loh ,S. E. Swirhun ,T. A. Schreyer ,R. M. Swanson ,and K. C. Saraswat ‘Current crowding effects and determination of specific contact resistivity from contact end resistance (CER) measurements’ ,IEEE Trans. Electron Devices ,ED-34 ,pp. 512–524 (1987).CrossRefGoogle Scholar
  43. [42]
    F. M. Klaassen ,P. T. J. Biermans ,and R. M. D. Velghe ,‘The series resistance of submicron MOSFETs and its effect on their characteristics’ ,Proc. ESSDERC 1988 J. De Physique ,pp. 257–260 (1988).Google Scholar
  44. [43]
    G. J. Hu ,C. Chang ,and Y. T. Chia ,‘Gate-voltage-dependent effective channel length and series resistance of LDD MOSFETs’ ,IEEE Trans. Electron Devices ,ED-34 pp. 2469–2475 (1987).CrossRefGoogle Scholar
  45. [44]
    S. Y. Chou and D. A. Antoniadis ,‘Relationship between measured and intrinsic transconductances of FETs’ ,IEEE Trans. Electron Devices ,ED-34 ,pp. 448–450 (1987).CrossRefGoogle Scholar
  46. [45]
    S. Cserveny ,‘Relationship between measured and intrinsic transconductances of MOSFETs’ ,IEEE Trans. Electron Devices ,ED-37 ,pp. 2413–2414 (1990).CrossRefGoogle Scholar
  47. [46]
    M. H. Seavey ,‘Source and drain resistance determination for MOSFETs’ ,IEEE Electron Device Lett., EDL-5 ,pp. 479–481 (1984).CrossRefGoogle Scholar
  48. [47]
    R. Shrivastava and K. Fitzpatrick ,‘A simple model for the overlap capacitance of a VLSI MOS device’ ,IEEE Trans. Electron Devices ,ED-29 ,1870–1875 (1982).CrossRefGoogle Scholar
  49. [48]
    E. W. Greeneich ,‘An analytical model for the gate capacitance of small-geometry MOS structures’ ,IEEE Trans. Electron Devices ,ED-30 ,pp. 1838–1839 (1983).CrossRefGoogle Scholar
  50. [49]
    T. Smedes and F. M. Klaassen ,Effects of the lightly doped drain configuration on capacitance characteristics of submicron MOSFETs‘ ,IEEE IEDM-90’, Technical Digest ,pp. 197–200 (1990).Google Scholar
  51. [50]
    N. D. Arora ,D. A. Bell ,and L. A. Bair ,‘An accurate method of determining MOSFET gate overlap capacitance’ ,Solid-State Electron., 35 ,pp. 1817–1822 (1992).CrossRefGoogle Scholar
  52. [51]
    S. W. Lee and R. C. Rennick ,‘A compact IGFET model-ASIM’ ,IEEE Trans. Computer-Aided Design ,CAD-7 ,pp. 952–975 (1988).CrossRefGoogle Scholar
  53. [52]
    S. Liu and L. W. Nagel ,‘Small-signal MOSFET models for analog circuit design’ IEEE J. Solid-State Circuits ,SC-17 ,pp. 983–998 (1982).CrossRefGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1993

Authors and Affiliations

  • Narain Arora
    • 1
  1. 1.Digital Equipment CorporationHudsonUSA

Personalised recommendations