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Statistical Modeling and Worst-Case Design Parameters

  • Narain Arora
Part of the Computational Microelectronics book series (COMPUTATIONAL)

Abstract

In integrated circuit technology, the final dimensions of all structures (transistors, capacitors, interconnecting wires, etc.) on finished wafers usually differ from their drawn (intended) dimensions due to several processing effects such as lateral expansion of local oxidation, imperfect etching, mask alignment tolerances, etc. It is observed, for example, in a 2 μm CMOS process, a polysilicon line drawn to be 2μm could be any where between 1.3–1.8 μm. Similarly, a 4 μm drawn metal line would turn out to be anywhere between 3.2–4.2 μm. Further, since transistor dimensions are determined by the width of the crossing polysilicon and by the lateral diffusion of the source and drain, transistor width to length ratio (W m /L m) can vary appreciably from the intended value. In addition to the line-width variations, there are many other process related variations such as changes in oxide thickness, sheet resistance, threshold voltage, etc., which result in the spread in device performance. Clearly, device parameters are subject to statistical variations due to manufacturing process disturbances. These variations affect the circuit performance dramatically. For example, changes in threshold voltage due to process variations will result in changes in transistor characteristics, which in turn affect DRAM access time and refresh rate, clock speed, etc., in digital circuits and op-amp gain in analog circuits. In the worst case the circuits might cease to function.

Keywords

Circuit Simulation VLSI Circuit Drain Voltage Versus Extract Model Parameter Principal Factor Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. Spence and R. S. Soin, Tolerance Design of Electronic circuits, Addison-Wesley Publishing Co., Reading, MA, 1988.Google Scholar
  2. [2]
    P. Yang and P. Chatterjee, ’statistical modeling of small geometry MOSFET, IEEE-IEDM82, Tech. Digest, pp. 286–289 (1982).Google Scholar
  3. [3]
    P. Cox, P. Yang, S. S. Mahant-Shetti, and P. Chatterjee, ’statistical modeling for efficient parametric yield estimation of MOS VLSI circuits’, IEEE Trans. Electron Devices, ED-32, pp. 471–478 (1985).CrossRefGoogle Scholar
  4. [4]
    N. Herr and J. J. Barnes, ’statistical circuit simulation modeling of CMOS VLSI’, IEEE Trans. Computer Aided Design, CAD-5, pp. 15–22 (1986).Google Scholar
  5. [5]
    J. P. Spoto, W. T. Coston, and C. P. Hernandez, ’statistical integrated circuit design and characterization’, IEEE Trans. Computer Aided Design, CAD-5, pp. 91–103 (1986).Google Scholar
  6. [6]
    T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, ’statistical performance modeling and parametric yield estimation of MOS VLSI’, IEEE Trans. Computer Aided Design, CAD-6, pp. 1013–1022 (1987).Google Scholar
  7. [7]
    P. Tuohy, A. Gribben, A. J. Walton, and J. M. Robertson, ‘Realistic worst-case parameters for circuit simulation’, IEEE Proa, 134, Pt. I, pp. 137–140 (1987).Google Scholar
  8. [8]
    S. Inohira, T. Shinmi, M. Nagata, T. Toyabe, and K. Iida, ‘A statistical model including parameter matching for analog integrated circuits simulation,’IEEE Trans. Computer Aided Design, CAD-4, pp. 621–628 (1985).Google Scholar
  9. [9]
    M. Pelgrom, A. Duinmaijer, and A. Welbers, ‘Matching properties of MOS transistor’, IEEE J. Solid-State Circuits, 24, pp. 1433–1439 (1989).CrossRefGoogle Scholar
  10. [10]
    C. Michael and M. Ismail, ’statistical modeling of device mismatch for analog MOS integrated circuits’, IEEE J. Solid-State Circuits, 27, pp. 154–166 (1992).CrossRefGoogle Scholar
  11. [11]
    L. A. Glasser and D. W. Doubberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley Publishing Co., Reading, MA, 1985.Google Scholar
  12. [12]
    W. Maly and A. J. Strojwas, ’statistical simulation of the IC manufacturing process’, IEEE Trans, on Computer Aided Design, CAD-1, pp. 120–131 (1982).CrossRefGoogle Scholar
  13. [13]
    S. R. Nassif, A. J. Strojwas, and S. W. Director, ‘FABRICHSII: A statistical based IC fabrication process simulator,’IEEE Trans, on Computer Aided Design, CAD-3, pp. 40–46 (1984). Also see Report (Feb. 1990) on FABRICS II: ‘A statistical simulator of the IC manufacturing process’, Department of Electrical Engineering, Carnegie-Mellon University, Pittsburgh, PA, 15213.CrossRefGoogle Scholar
  14. [14]
    S. R. Nassif, A. J. Strojwas, and S. W. Director, ‘A methodology for worst-case analysis of integrated circuits’, IEEE Trans, on Computer Aided Design, CAD-5, pp. 104–113 (1986).CrossRefGoogle Scholar
  15. [15]
    D. G. Rees, ‘Foundations of Statistics’ ,Chapman and Hall, New York, 1987.Google Scholar
  16. [16]
    R. E. Walpole and R. H. Myers, Probability and Statistics for Engineers and Scientists, McGraw Hill, New York, 1976.Google Scholar
  17. [17]
    C. W. Helstrom, Probability and Stochastic Processes for Engineers ,Macmillan Publishing Company, New York, 1984.Google Scholar
  18. [18]
    N. D. Arora and L. M. Richardson, ‘MOSFET modeling for circuit simulation’in Advanced MOS Device Physics (N. G. Einspruch and G. Gildenblat, eds.), VLSI Electronics: Microstructure Science, Vol. 18, pp. 236–276, Academic Press Inc., New York, 1989.Google Scholar
  19. [19]
    V. Bernett and T. Lewis, Outliers in Statistical Data ,John Wiley &Sons, New York, 1978.Google Scholar
  20. [20]
    J. A. Power, A. Mathewson, and W. A. Lane, ‘MOSFET statistical parameter extraction using multivariate statistics’, 1991 Int. Conf. Microelectronics Test Structures, 4, pp. 209–214 (1991).CrossRefGoogle Scholar
  21. [21]
    M. Bolt, M. Rocchi, and J. Engel, ‘Realistic statistical worst-case simulations of VLSI circuits’, IEEE Trans. Semicond. Manuf., 4, pp. 193–198 (1991).CrossRefGoogle Scholar
  22. [22]
    D. A. Divekar, R. W. Dutton, and W. J. McCalla, ‘Experimental study of Gummel-Poon Model parameter correlations for bipolar junction transistors’, IEEE Journal of Solid-State Circuits, SC-12, pp. 552–559 (1977).CrossRefGoogle Scholar
  23. [23]
    A. A. Afifi and V. Clark, Computer-Aided Multivariate Analysis ,Lifetime Learning Publications, Belmont, CA, 1984.Google Scholar
  24. [24]
    J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design ,Van Nostrand Rienhold Company, New York, 1983.Google Scholar
  25. [25]
    D. F. Morrison, Multivariate Statistical Methods ,McGraw-Hill Book Company, New York, 1976.MATHGoogle Scholar
  26. [26]
    R. A. Johnson and D. W. Wichern, Applied Multivariate Statistical Analysis ,Prentice-Hall Inc., Englewood Cliffs, New Jersey, 1982.MATHGoogle Scholar
  27. [27]
    M. E. Johnson, Multivariate Statistical Simulation ,John Wiley &Sons, New York, 1987 (P-52).MATHGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1993

Authors and Affiliations

  • Narain Arora
    • 1
  1. 1.Digital Equipment CorporationHudsonUSA

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