Resynchronization Interfaces: Sources of Metastability Errors in Computing Systems

  • D. Del Corso
  • F. Maddaleno
  • M. Minichino
  • E. Pasero
Part of the Dependable Computing and Fault-Tolerant Systems book series (DEPENDABLECOMP, volume 4)


In computing systems, bistable flip-flops are used to store binary variables and to resynchronize asynchronous signals in the various interfaces. These bistable devices can be driven by specific input conditions into a metastable state, where they may remain for a time predictable only in a statistical way. An output in metastability may introduce random errors in the connected circuits. Being related with basic time-decision ambiguity, this phenomenon is unavoidable. Viable ways to decrease the metastable hazard are the technology improvement, a correct design methodology, and/or an increase of the decision delay. The metastable hazard increases with the evolution of the technology, as the relative indetermination of propagation delays becomes more significant. This work presents the fundamental concept of time-decision ambiguity and shows that significant error bursts may occur in presence of “almost equal” clock frequencies; the interface specifications of some multiprocessor buses (VME, Multibus 2, Nubus, Futurebus) and serial communications (Ethernet) are then analyzed from this point of view.


Metastable State Clock Frequency Flip Flop Clock Period Burst Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag/Wien 1991

Authors and Affiliations

  • D. Del Corso
    • 1
  • F. Maddaleno
    • 1
  • M. Minichino
    • 2
  • E. Pasero
    • 3
  1. 1.Dipartimento di ElettronicaPolitecnico di TorinoTorinoItaly
  2. 2.ENEARomaItaly
  3. 3.Dip di Ing. ElettronicaII UniversitàRomaItaly

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