Abstract
The parameters of a compact model are in general dependent on the geometry of the device and on the technological process steps. The geometry of the device is mainly characterized by the lateral dimensions of the junctions in bipolar transistors and by the channel length and width in MOS transistors. The dimensions must be known in silicon because only the real dimensions are electrically significant. They are determined by the dimensions of the mask, corrected for such effects as outdiffusion, underetching, misalignment of masks, encroachment of isolation oxides, etc.
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References
R. Berry: Correlation of Diffusion Process Variations with Variations in Electrical Parameters of Bipolar Transistors. Proc. IEEE 57, 1513 (1969).
R. W. Dutton, D. A. Divekar: Bipolar Models for Statistical IC Design. In: Process and Device Modeling for Integrated Circuit Design ( F. van de Wiele, W. L. Engl, P. G. Jespers, eds.). Noordhoff, Leyden (1977).
C. J. B. Spanos, S. W. Director: Parameter Extraction for Statistical IC Process Characterization. IEEE Trans. Comp.-Aid. Des. CAD-5, 66 (1986).
P. Yang, et al.: An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design. IEEE Trans. Comp.-Aid. Des. CAD-5, 5 (1986).
P. Cox, et al.: Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits. IEEE Trans. Electr. Dev. ED-32, 471 (1985).
P. J. Rankin: Statistical Modelling for Integrated Circuits. IEEE Proc. 129, 186 (1982).
N. Herr, B. Garbs, J. J. Barnes: A Statistical Modeling Approach for Simulation of MOS VLSI Circuit Designs. lEDM Techn. Digest (1982), p. 290 (paper [11.5).
Ph. Balaban, J. J. Golembeski: Statistical Analysis for Practical Circuit Design. IEEE Trans. Circ. Syst. CAS-22,100(1975).
S. Inohira, et al: Statistical Model Including Parameter Matching for Analog Integrated Circuits Simulation. Trans. Electr. Dev. ED-32, 2177 (1985).
P. M. Solomon, D. D. Tang: Bipolar Circuit Scaling. IEEE Int. Solid-St. Circ. Conf. (1979), p. 86 (paper WPM 8. 4 ).
P. A. H. Hart, T. v. ’t Hof, F. M. Klaassen: Device Down Scaling and Expected Circuit Performance. IEEE J. Solid-St. Circ. SC-14, 343 (1979).
T. Smedes: Optimization and Down Scaling of Processes for ECL Circuits. Master Thesis, Technical University, Eindhoven (1986).
H. C. de Graaff, W. J. Kloosterman: New Formulation of the Current and Charge Relations in Bipolar Transistor Modeling for CACD Purposes. IEEE Trans. Electr. Dev. ED-32, 2415 (1985).
J. W. Slotboom: Computer-Aided Two-Dimensional Analysis of Bipolar Transistors. IEEE Trans. Electr. Dev. ED-20, 669 (1973).
N. Shiono: Emitter Perimeter-to-Area Ratio Effects on High-Frequency Transistor Current Gain and Its Degradation. Jap. J. A. P. 18, 1097 (1979).
G. A. M. Hurkx: On the Sidewall Effects in Submicrometer Bipolar Transistors. IEEE Trans. Electr. Dev. ED-34, 1939 (1987).
R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli: A Survey of Optimization Techniques for Integrated-Circuit Design. Proc. IEEE 69, 1334 (1981).
A. M. Mood, F. A. Graybill, D. C. Boes: Introduction to the Theory of Statistics, 3rd Ed. McGraw-Hill, Tokyo (1974).
A Papoulis: Probability, Random Variables and Stochastic Processes. McGraw-Hill, Kogagusha, Tokyo (1965).
P. Yang, P. Chatterjee: Statistical Modelling of Small Geometry MOSFETs. Techn. Digest IEDM 286 (1982), (paper [11.4).
K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland: Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design. IEEE J. Solid-State Circ. SC-21, 1057 (1986).
W. Maly, A. Strojwas: Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comp.-Aid. Des. CAD-1, 120 (1982).
S. R. Nassif, A. Strojwas, S. W. Director: Fabrics II, A Statistically Based IC Fabrication Process Simulator. IEEE Trans. Comp.-Aid. Des. CAD-3, 40 (1984).
J. B. Shyu, G. Temos, F. Krummenacher: Random Error Effects in Matched MOS Capacitors and Current Sources. IEEE Journal of Solid-State Circuits SC-19, 948–955 (1984).
M. J. M. Pelgrom, A. C. J. Duinmayer: Matching Properties of MOS Transistors. Digest ESSCIRC (1988).
M. J. M. Pelgrom: Delay Lines with Surface Channel Charge-Coupled Devices. Ph.D. Thesis, University of Technology, Twente, The Netherlands (1988).
M. J. B. Bolt, A. Trip, H. J. Verhagen: Statistical Worst-Case MOS Parameter Extraction. Proceedings on Microelectronic Test Structures. Edinburgh (1989).
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de Graaff, H.C., Klaassen, F.M. (1990). Process and Geometry Dependence, Optimization and Statistics of Parameters. In: Compact Transistor Modelling for Circuit Design. Computational Microelectronics. Springer, Vienna. https://doi.org/10.1007/978-3-7091-9043-2_11
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DOI: https://doi.org/10.1007/978-3-7091-9043-2_11
Publisher Name: Springer, Vienna
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