Advertisement

A History of Research in Fault Tolerant Computing at the Grenoble University

  • René David
  • Bernard Courtois
  • Gabrièle Saucier
Conference paper
Part of the Dependable Computing and Fault-Tolerant Systems book series (DEPENDABLECOMP, volume 1)

Abstract

This paper presents the research in Fault-Tolerant Computing at the Grenoble University for over fifteen years. The main topics are random testing of digital circuits, testing VLSI, self-checking circuits, and validation of high dependability systems.

Keywords

Fault Tolerant Random Testing Digital Circuit Linear Feedback Shift Register Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [Te 74]
    R. Tellez-Giron “Contribution à l’Etude du test aléatoire des systèmes logiques” Docteur-Ingénieur Thesis, Grenoble University, March 1974.Google Scholar
  2. [TeDa 74]
    R. Tellez-Giron, David R., “Random fault detection in logical networks” in IFAC Int. Symp. on Discrete Systems Dig., Zinatne, R.ga, USSR, vol. 2, Oct 1974, pp. 232–241Google Scholar
  3. [RoSa 75]
    C. Robach, G. Saucier, “Diversified test methods for local control units” IEEE Trans, on Computers, Vol. C-24, N. 5, May 1975, pp. 562–567.CrossRefGoogle Scholar
  4. [DaBl 76]
    R. David, G. Blanchet, “About random fault detection in combinational networks” IEEE Trans, on Computers Vol. C-25, pp. 659–664, June 1976.CrossRefMathSciNetGoogle Scholar
  5. [RoSa 76]
    C. Robach, G. Saucier, J. Lebrun, “Processor testability and design consequences”, IEEE Trans, on Computers, Vol. C-25, N. 6, June 1976, pp. 645–652.CrossRefGoogle Scholar
  6. [DeSi 76]
    P. Deschizeaux, M. Silva-Suarez, G. Nicoud, F. Martin “Statistical Fault-location in Logical Circuits”, 6th Fault-Tolerant Computing Symposium, Pittsburg, June 1976, pp. 88. 92Google Scholar
  7. [CaMi 78]
    P. Caspi, A. Mili, C. Robach, “An information measure on nets-Application to testability of digital systems”, Information and Systems, ed. by B. Dubuisson, New York, Pergamon, 1978, pp. 35–39.Google Scholar
  8. [ThDa 78]
    P. Thevenod-Fosse, R. David, “Test aléatoire des mémoires”, Rev. Française d’Automatisme, d’informatique, de Recherche. Op., Vol. 12, N. J1, pp. 43–61., 1978Google Scholar
  9. [RoSa 78]
    C. Robach, G. Saucier, “Dynamic testing of control units”, IEEE Trans, on Computers, Vol. C-27, N. 7 July 1978, pp. 617–623.CrossRefMathSciNetGoogle Scholar
  10. [RoSa 79]
    C. Robach, G. Saucier, C. Aleonard, “Microprocessor systems testing: a review and future prospects” EUROMICRO Journal, Vol. 5, N. l, January 1979, pp. 31–37.Google Scholar
  11. [RoSa 80]
    C. Robach, G. Saucier, “Application oriented microprocessor test method”, 10th Fault-Tolerant Computing Symposium, Kyoto ( Japan ), October 1980, pp. 121–125.Google Scholar
  12. [DaTh 80]
    R. David, P. Thevenod-Fosse, “Minimal detection sequences: application to random testing”, IEEE Trans, on computers, Vol. C-29, June 1980, pp. 514–518.Google Scholar
  13. [Da 80]
    R. David, “Testing by Feedback Shift Registers”, IEEE Trans, on Computers, Vol. C-29, July 1980, pp. 668–673.Google Scholar
  14. [ViDa 80]
    J. Viaud, R. David “Sequentially self-checking Circuits”, 10th Fault Tolerant Computing Symposium. Kyoto, JAPAN-October 1980, pp. 263–268Google Scholar
  15. [CaPu 81]
    P. Caspi, J. Pulou, “A method for improving the reliability of functionally distributed networks”, Journal of Digital Systems, Vol. 4, 1981.Google Scholar
  16. [DaTh 81]
    R. David, P. Thevenod-Fosse, “Random Testing of Integrated Circuits”, IEEE Trans, on Instrumentation and Measurement, Vol. IM-30, March 1981, pp. 20–25Google Scholar
  17. [ThDa 81]
    P. Thevenod-Fosse, R. David, “Random Testing of the Data Processing Section of a Microprocessor, 11th Fault-Tolerant Computing Symposium”, Portland, June 1981, pp. 275–280.Google Scholar
  18. [Co 81–1]
    B. Courtois, “Failure mechanisms, fault-hypotheses and analytical testing of LSI-NMOS (HMOS) circuits” VLSI 81, University of Edinburgh, 18. 21. 8. 81, Academic PressGoogle Scholar
  19. [Co 81–2]
    B. Courtois, “On-line oriented functional testing of control sections of integrated CPU”, EUROMICRO Symposium, Paris, September 1981, FranceGoogle Scholar
  20. [Co 81–3]
    B. Courtois, “A methodology for on-line testing of microprocessors” 11th Fault Tolerant Computing Symposium, Portland, June 81, USAGoogle Scholar
  21. [Co 81–4]
    B. Courtois, “SKALP Skeleton Architecture for fault tolerant distributed processing” EUROMICRO Journal, Vol. 7, N. 5, May 1981Google Scholar
  22. [Co 81–5]
    B. Courtois, “Safety Availability and Maintenance Evaluation of Redundant Systems” Digital Processes-1981Google Scholar
  23. [Co 82]
    B. Courtois “Performance modeling of partially self-checking systems”, 12th Fault Tolerant Computing Symposium, Santa Monica, June 1982, USAGoogle Scholar
  24. [MaCo 82]
    P. Marchal, B. Courtois, “On detecting the hardware failures disrupting programs in microprocessors” 12th Fault Tolerant Computing Symposium, Santa Monica, June 1982, USAGoogle Scholar
  25. [BeCo 82]
    M. Ben Romdhane, B. Courtois, “Error confinement/data recovery in distributed systems”, 2nd Symposium on reliability in distributed software and data base systems. Pittsburg, July 1982, USA.Google Scholar
  26. BeSa 82] C. Bellon, G. Saucier, “Protection against external errors in a dedicated system”, IEEE trans, on Computers, Vol. C-31, N. 4, April 82.Google Scholar
  27. [Be 82]
    C. Bellon et alt., “Automatic generation of microprocessor test programs”, 19th Design Automation Conference Proc. pp. 566–573, Las Vegas Nevada, June 1982.Google Scholar
  28. [Pi 82]
    E. Pilaud, “Design and validation of high dependability computer systems”, Ph. D. Thesis, INPG, Grenoble, November 1982.Google Scholar
  29. [BaBe 83]
    G. Baille, L. Bergher, B. Courtois, J. Laurent, C. Rubat Du Merac “Testing for failure analysis: new tools and new test methods”, 13th Fault Tolerant Computing Symposium. Milano, June 1983, ItalyGoogle Scholar
  30. [ThDa 83]
    P. Thevenod-Fosse, R. David, “Random Testing of the Control Section of a Microprocessor”, 13th Fault-Tolerant Computing Symposium, Milan (I), June 1983, pp. 366–373.Google Scholar
  31. [DeTh 84]
    H. Deneux, P. Thevenod-Fosse, L. Beghin, “Test aléatoire de circuits développés par le CNET/CNS”, 4th Conference on Reliability and Maintainability, Perros-Guirec (F), May 1984.Google Scholar
  32. [NiJa 84]
    M. Nicolaidis, I. Jansch, B. Courtois, “Strongly code disjoint checkers”, 14th Fault-Tolerant Computing Symposium Orlando, June 1984, USAGoogle Scholar
  33. [JaCo 84]
    I. Jansch, B. Courtois, “On the design of checkers based on analytical fault hypotheses”, ESSIRC 1984. Edinburgh. August 1984, United KingdomGoogle Scholar
  34. [BaCo 84]
    D. Bashiera, B. Courtois, “Testing CMOS: A challenge ?”, VLSI Design, October 1984Google Scholar
  35. [RoMa 84]
    C. Robach, P. Malecha, G. Michel, “CATA: a Computer Aided Test Analysis System” IEEE Design and Test of Computers, Vol. 1, N. 2, May 1984, pp. 68–79.CrossRefGoogle Scholar
  36. [CaKo 84]
    P. Caspi, E. F. Kouka, “Stopping rules for a debugging process based on different software reliability models”, 14th Fault-Tolerant Computing Symposium, Orlando, June 1984.Google Scholar
  37. [BeVe 84]
    C. Bellon, R. Velazco, “Taking into account asynchronous signals in functional test of complex circuits”, 21st Design Automation Conference Proc., pp. 490–496, Albuquerque, New Mexico, june 1984.Google Scholar
  38. [BeVe 84b]
    C. Bellon, R. Velazco, “Hardware and software tools for microprocessor functional test” International Test Conference 1984, pp. 804–810, Philadelphia, October 1984.Google Scholar
  39. [JaSa 84]
    C. Jay, G. Saucier, “A testable microprocessor for process control”, ICCD 84, pp. 284–289, New York, October 1984.Google Scholar
  40. [VeKo 85]
    R. Velazco, E. Kolokithas, H. Ziade, “A microprocessor approach. allowing fault localization” International Test Conference 1985, pp. 737–743, Philadelphia, November 1985.Google Scholar
  41. [Co 85]
    B. Courtois, “Computer Architecture Group. Activity Report 1985” IMAG/TIM3 Report 1985Google Scholar
  42. [Ma 85]
    P. Marchai, “Functional fault hypotheses for the test of microprocessors internal bus malfunctions”. 15th Fault Tolerant Computing Symposium, Ann Arbor, Michigan, June 1985 USA.Google Scholar
  43. [JaCo 85]
    I. Jansch, B. Courtois, “Strongly Language Disjoint checkers”, 15th Fault Tolerant Computing Symposium, Ann Arbor, Michigan, June 1985, USAGoogle Scholar
  44. [Ni 85–1]
    M. Nicolaidis, “An efficient built-in self test scheme for functional test of embedded RAMs.” 15th Fault Tolerant Computing Symposium, Ann Arbor, Michigan, June 1985, USAGoogle Scholar
  45. [Ni 85–2]
    M. Nicolaidis, “Evaluation of a self-checking version of the MC68000 microprocessor”, 15th Fault Tolerant Computing Symposium, Ann Arbor, Michigan, June 1985, USAGoogle Scholar
  46. [NiCo 85]
    M. Nicolaidis, B. Courtois, “Layout rules for the design of self-checking circuits” VLSI 85, Tokyo, Japan, August 1985Google Scholar
  47. [Al 86]
    M. Aliouat, “Reprise de processus dans un environnement distribué après pannes matérielles transitoires ou permanents”, Thesis INPG, April 1986Google Scholar
  48. [JeVa 86]
    A. Jerraya, P. Varinot, R. Jamier, B. Courtois, “Principles of the SYCO compiler”, Design Automation Conference, Las Vegas, June 1986, USAGoogle Scholar
  49. [NiCo 86]
    M. Nicolaidis, B. Courtois, “Design of NMOS Strongly Fault Secure Circuits using unidirectional errors detecting codes” 16th Fault Tolerant Computing Symposium, Vienna, July 1986. AustriaGoogle Scholar
  50. [OsNi 86]
    A. Osseiran, M. Nicolaidis, J. P. Schoellkopf, B. Courtois, B. Le Trunc, D. Bied Charreton “Design of a self-checking microprocessor for real-time application in transportation systems”, 5th IFAC/IFIP/IFORS, Vienna, July 1986. AustriaGoogle Scholar
  51. [Ni 86]
    M. Nicolaidis, “An unified built-in self-test scheme: UBIST”, ESSIRC Conference Deft, Septembre 1986, NetherlandsGoogle Scholar
  52. [BeLa 86]
    L. Bergher, J. Laurent, J. P. Collin, B. Courtois “Towards automatic failure analysis of complex ICs through e-beam testing”, International Test Conference, Washington, September 1986, USAGoogle Scholar
  53. [GuMi 86]
    I. Guiguet, D. Micollet, J. Laurent, B. Courtois “Electron beam observability and controlability for the debugging of integrated circuits”, ESSIRC Conference, Delft, September 1986. NetherlandsGoogle Scholar
  54. [BaCo 86]
    D. Bachiera, B. Courtois, “Advances in fault modeling and test pattern generation”, International Conference on Computer Design, New York, October 1986.Google Scholar
  55. [FeDa 86]
    X. Fedi, R. David, “Some Experimental Results from Random Testing of Microprocessors”, IEEE Trans, on Instrumentation and Measurement, Vol. IM-35, March 1986, pp. 78–86.Google Scholar
  56. [AbTh 86]
    Z. Abazi, P. Thevenod-Fosse, “Markov Models for the Random Testing Analysis of Cards”, 16th Fault-Tolerant Computing Symposium, Vienna (A), July 1986, pp. 272–277.Google Scholar
  57. [FuDa 86]
    A. Fuentes, R. David, B. Courtois, “Random Testing versus Deterministic Testing for RAMs”, 16th 16th Fault-Tolerant Computing Symposium, Vienna (A), July 1986, pp. 266–271.Google Scholar
  58. [Da 86]
    R. David, “Signature Analysis for Multiple output Circuits”, IEEE Trans, on Computers, Vol. C-35, September 1986, pp. 830–837.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1987

Authors and Affiliations

  • René David
    • 1
  • Bernard Courtois
    • 2
  • Gabrièle Saucier
    • 3
  1. 1.LAG/INPGSt Martin d’HeresFrance
  2. 2.TIM3-IMAG/INPGGrenoble CEDEXFrance
  3. 3.LCS-IMAG/INPGGrenoble CedexFrance

Personalised recommendations