Actually, it is rather difficult to present examples of simulations which are both interesting for readers with experience in numerical modeling and informative for readers with just general interest in modeling but without specialized knowledge of device physics. I have chosen two examples which are intended as a fair trade-off between these objectives.


Threshold Voltage Electrostatic Potential Impact Ionization Hole Concentration Depletion Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [9.1]
    Adler, M. S., Temple, V. A. K., Rustay, R. C.: Theoretical Basis for Field Calculations on Multi-Dimensional Reverse Biased Semiconductor Devices. Solid-State Electron. 25, No. 12, 1179–1186 (1982).CrossRefGoogle Scholar
  2. [9.2]
    Antoniadis, D. A., Hansen, S. E., Dutton, R. W.: SUPREM II-a Program for IC Process Modeling and Simulation. Report 5019–2, Stanford University, 1978.Google Scholar
  3. [9.3]
    Barnes, J. J., Shimohigashi, K., Dutton, R. W.: Short-Channel MOSFET’s in the Punchthrough Current Mode. IEEE Trans. Electron Devices ED-26, 446–453 (1979).CrossRefGoogle Scholar
  4. [9.4]
    Chamberlain, S. G., Husain, A.: Three-Dimensional Simulation of VLSI MOSFET’s. Proc. Int. Electron Devices Meeting, pp. 592–595 (1981).Google Scholar
  5. [9.5]
    Chynoweth, A. G.: Ionization Rates for Electrons and Holes in Silicon. Physical Review 109, 1537–1540 (1958).CrossRefGoogle Scholar
  6. [9.6]
    Demoulin, E., Greenfield, J. A., Dutton, R. W., Chatterjee, P. K., Tasch, A. F.: Process Statistics of Submicron MOSFET’s. Proc. Int. Electron Devices Meeting, pp. 34–37 (1979).Google Scholar
  7. [9.7]
    Franz, A. F., Franz, G. A., Selberherr, S., Ringhofer, C., Markowich, P.: Finite Boxes — A Generalization of the Finite Difference Method Suitable for Semiconductor Device Simulation. IEEE Trans. Electron Devices ED-30, No. 9, 1070–1082 (1983).CrossRefGoogle Scholar
  8. [9.8]
    Franz, G. A., Franz, A. F., Selberherr, S., Markowich, P.: A Quasi Three Dimensional Semiconductor Device Simulation Using Cylindrical Coordinates. Proc. NASECODE III Conf., pp. 122–127. Dublin: Boole Press 1983.Google Scholar
  9. [9.9]
    Greenfield, J. A., Dutton, R. W.: Nonplanar VLSI Device Analysis Using the Solution of Poisson’s Equation. IEEE Trans. Electron Devices ED-27, 1520–1532 (1980).CrossRefGoogle Scholar
  10. [9.10]
    Kotani, N., Kawazu, S.: Computer Analysis of Punch-Through in MOSFET’s. Solid-State Electron. 22, 63–70 (1979).CrossRefGoogle Scholar
  11. [9.11]
    Kotani, N., Kawazu, S.: A Numerical Analysis of Avalanche Breakdown in Short-Channel MOSFET’s. Solid-State Electron. 24, 681–687 (1981).CrossRefGoogle Scholar
  12. [9.12]
    Müller, W., Risch, L., Schütz, A.: Analysis of Short Channel MOS Transistors in the Avalanche Multiplication Regime. IEEE Trans. Electron Devices ED-29, No. 11, 1778–1784 (1982).CrossRefGoogle Scholar
  13. [9.13]
    Schütz, A., Selberherr, S., Pötzl, H. W.: A Two-Dimensional Model of the Avalanche Effect in MOS Transistors. Solid-State Electron. 25, 177–183 (1982).CrossRefGoogle Scholar
  14. [9.14]
    Schütz, A., Selberherr, S., Pötzl, H. W.: Analysis of Breakdown Phenomena in MOSFET’s. IEEE Trans. Computer-Aided-Design of Integrated Circuits CAD-1, 77–85 (1982).CrossRefGoogle Scholar
  15. [9.15]
    Selberherr, S., Schütz, A., Pötzl, H. W.: MINIMOS — a Two-Dimensional MOS Transistor Analyzer. IEEE Trans. Electron Devices ED-27, 1540–1550 (1980).CrossRefGoogle Scholar
  16. [9.16]
    Selberherr, S., Schütz, A., Pötzl, H.: Investigation of Parameter Sensitivity of Short Channel MOSFET’s. Solid-State Electron. 25, 85–90 (1982).CrossRefGoogle Scholar
  17. [9.17]
    Selberherr, S., Schütz, A., Pötzl, H.: Two Dimensional MOS-Transistor Modeling. In: Process and Device Simulation for Integrated Circuit Design, pp. 490–581. The Hague: Martinus Nijhoff 1983.Google Scholar
  18. [9.18]
    Toyabe, T., Yamaguchi, K., Asai, S., Mock, M. S.: A Numerical Model of Avalanche Breakdown in MOSFET’s. IEEE Trans. Electron Devices ED-25, 825–832 (1978).CrossRefGoogle Scholar
  19. [9.19]
    Troutman, R. R.: VLSI Limitations from Drain-Induced Barrier Lowering. IEEE Trans. Electron Devices ED-26, 461–469 (1979).CrossRefGoogle Scholar
  20. [9.20]
    Van Overstraeten, R., DeMan, H.: Measurement of the Ionization Rates in Diffused Silicon p-n Junctions. Solid-State Electron. 13, 583–608 (1970).CrossRefGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1984

Authors and Affiliations

  • Siegfried Selberherr
    • 1
  1. 1.Institut für Allgemeine Elektrotechnik und ElektronikTechnische Universität WienAustria

Personalised recommendations