VLSI Standard Cell Placement by Parallel Hybrid Simulated-Annealing and Genetic Algorithm

  • Karl Kurbel
  • Bernd Schneider
  • Kirti Singh
Conference paper


Placement of standard cells is a part of physical VLSI chip design. In order to achieve high performance, area of the chip and lengths of wires connecting cells have to be minimized. In the placement step, the goal is to place cells in such a way that total wire-length is as short as possible. Since this problem is NP-hard, heuristic techniques have to be applied. Modern approaches include simulated annealing and genetic algorithms. In this paper, we discuss those methods and show that they can be improved by combination. A heuristic technique called parallel recombinative simulated annealing (PRSA) is described. It integrates features of both simulated annealing and genetic algorithms. Behavior of PRSA is studied with respect to different parameter settings.


Genetic Algorithm Simulated Annealing Standard Cell Heuristic Technique Communication Topology 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag/Wien 1995

Authors and Affiliations

  • Karl Kurbel
    • 1
  • Bernd Schneider
    • 1
  • Kirti Singh
    • 2
  1. 1.Institute of Business InformaticsUniversity of MuensterMuensterGermany
  2. 2.Institute of Computer Science, Electronics and InstrumentationDevi Ahilya UniversityIndoreIndia

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