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3-D Topography Simulation Using Surface Representation and Central Utilities

  • A. R. Neureuther
  • R. H. Wang
  • J. J Helmsen
  • J. F. Sefler
  • E. W. Scheckler
  • R. Gunturi
  • Rex Winterbottom

Abstract

There are major opportunities for new algorithms and system integration concepts in TCAD systems which can be met by developing centralized utilities. Suitable purpose-built high performance algorithms for surface representation based simulation developed in connection with SAMPLE-3D are described. An exploratory centralized services system called the Berkeley Topography Utilities has been developed for studying the continuum of flexible choices between reusing these purpose-built algorithms and robust general-purpose solid modeling operations. This system links code from SAMPLE-3D, SIMPL, the IBM Geometry Engine serving as -a solid modeler, and a 2-D shock tracker. The BTU organization into hierarchial views, the use of surface direction monotonicity for speed enhancement, and a geometry tagging method for process trace-back are described.

Keywords

Surface Representation Optical Lithography Solid Extraction Triangulate Surface Polysilicon Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    D. Boning et al., “Developing and Integrating TCAD Applications with the Semiconductor Wafer Representation,” NUPAD IV, IEEE92TH0424–2, May 1992.Google Scholar
  2. [2]
    For information on the TCAD Work Bench contact Sematech in Austin, TX.Google Scholar
  3. [3]
    TCAD tools are available from Technology Modeling Associates, Silvaco, Dawn Technoloies, SIGMA-C, FINLE Technologies, Integrated Systems Engineering, Vector Technologies, and others.Google Scholar
  4. [4]
    W. G. Oldham, S. N. Nandgaonkar, A. R. Neureuther, and M. M. O’Toole, “A General Simulator for VLSI Lithography and Etching Processes: Part I-Application to Projection Lithography,” IEEE Trans. on Electron Devices, Vol. ED-26, No. 4, pp. 717–722 April 1979.CrossRefGoogle Scholar
  5. [5]
    K. Lee, Y. Sakai and A.R. Neureuther, “Topography Dependent Step Coverage Resistance Simulation for VLSI Design,” 1982 Symposium on VLSI Technology, Proceedings pp. 61–62, Oiso, Japan, Sept. 1–3, 1982.Google Scholar
  6. [6]
    G.M. Koppelman et al., IBM J. Res. Develop. Vol. 27, pp. 149–163, Mar. 1983.CrossRefGoogle Scholar
  7. [7]
    C.P. Ho et al., IEEE Trans. on Electron Devices, Vol. ED-30, No. 11, pp. 1438–1453, Nov. 1983.CrossRefGoogle Scholar
  8. [8]
    J. Lorenz et al., IEEE Trans. on Electron Devices, Vol. ED-32, No. 10, pp. 1977–1986, Oct. 1985.CrossRefGoogle Scholar
  9. [9]
    C.H. Corbex, A.F. Gerodolle, S.P. Martin, and A.R. Poncet, IEEE Trans. CAD. vol. 7 no. 4, pp. 489–500, April 1988.Google Scholar
  10. [10]
    S.G. Duvall, IEEE Trans. on Computer-Aided Design, Vol. CAD-7, No. 7, pp., 41–754, Jul. 1988.CrossRefGoogle Scholar
  11. [11]
    K. Kato, et al. “A Supervised Simulation System for Process and Device Designs based on Geometrical Data Interface,” IEEE Transactions on Electron Devices, vol ED-34, pp. 2049–2058, Oct. 1987.Google Scholar
  12. [12]
    Alexander S. Wong, “An Integrated Graphical Environment for Operating IC Process Simulators,” M.S. Thesis, University of-California, Berkeley, May 1989. UCB/ERL M89/67.Google Scholar
  13. [13]
    D.C. Cole, et al., Solid-State Electronics, vol. 33, no. 6, pp. 591–623, 1990.CrossRefGoogle Scholar
  14. [14]
    P. Lamb, C. Hegarty, N. Hitschfeld, W. Fichtner, “Generating Solid Models for VLSI Process and Device Simulation,” NUPAD-IV, Seattle, WA, May 1992, pp. 175–180.Google Scholar
  15. [15]
    M.R. Pinto, D.M. Boulin, C.S. Rafferty, R.K. Smith, W.M. Coughran,Jr., I.C. Kizilyalli, and M.J. Thoma, “Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation, ” IEDM’92 Tech Digest, Dec 1992, pp 923–926.Google Scholar
  16. [16]
    F. Fasching, W. Tuppa, S. Selberherr, IEEE Trans. CAD, vol. 13, pp. 72–81, Jan 1994.Google Scholar
  17. [17]
    Z.H. Sahul, R.W. Dutton, and M. Noe11, “Grid and Geometry Techniques for Multi-Layer Process Simulation,” Proc. of SISDEP-5, Vienna, Austria; Sept. 1993, pp 417–420.Google Scholar
  18. [18]
    C. Yang, M.D. Giles, “Architecture and Implementation of 3D Field Support for Semiconductor Wafer Representation,” Proc of NUPAD V, June 1994.Google Scholar
  19. [19]
    M. Law, World Wide Web Document http://www.eel.ufl.edu/law/manual/Intro.html
  20. [20]
    P.I. Hagouel and A.R. Neureuther, “Modeling of X-ray Resists for High Resolution Lithography”, ACS Organic Coating and Plastics Preprints, Vol.35, No.2, pp.258–265, August 1975 (for 3-D vector ray-trace formulation) and in Ph.D. Thesis, UC Berkeley 1976.Google Scholar
  21. [21]
    F. Jones and J. Paraszczak, “RD3D (Computer Simulation of Resist Development in Three Dimensions),” IEEE Trans. Electron Devices, vol. ED-28, no. 12, pp. 1544–1552, December 1981.CrossRefGoogle Scholar
  22. 122]
    T. Matsuzawa, T. Ito, and H. Sunami, “Three-dimensional Photoresist Image Simulation on Flat Surfaces,” IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1781–1783, September 1985.CrossRefGoogle Scholar
  23. [23]
    L. Jia, W. Jian-kun and W. Shao-jun, “Three-Dimensional Development of Electron Beam Exposed Resist Patterns Simulated Using Ray Tracing Model,” Microelectronics Engineering, vol. 6, pp. 147–151, 1987.CrossRefGoogle Scholar
  24. [24]
    A. Moniwa, T. Matsuzawa, T. Ito, and H Sunami, “A Three-Dimensional Photoresist imaging process Simulator for Strong Standing-Wave Effect Environment,” IEEE Trans on CAD, vol. CAD-6, no. 3, pp. 431–437, May 1987.Google Scholar
  25. [25]
    Y. Hirai, S. Tomida, K. Ikeda, M. Sasago, M. Endo, S. Hayama, and N. Nomura, “Three Dimensional Process Simulation for Photo and Electron Beam Lithography and Estimation of Proximity Effects,” Symposium on VLSI Technology, Digest of Technical papers, p. 15, 1987.Google Scholar
  26. [26]
    E. Barouch, B. Bradie, H. Fowler and S. Babu, “Three-Dimensional Modeling of Optical lithography for Positive Photoresists,” Interface ‘89: Proceedings of KTI Microelectronics Seminar, pp. 123–136, Nov. 1989.Google Scholar
  27. [27]
    J. Bauer, W. Mehr, and U. Glaubitz, “Simulation and Experimental Results in 0.6 um Lithography using an i-Line Stepper,” Proceedings of SPIE: Optical/ laser Microlithography III, vol. 1264, pp. 431–445, march 1990.Google Scholar
  28. [28]
    W. Henke, D. Mewes, M. Weiss, G. Czech, and R. Schiessi-Hoyler, “Simulation of Defects in 3-Dimensional Resist profiles in Optical Lithography,” Microelectronics Engineering, vol. 13, pp. 497–501, 1991.CrossRefGoogle Scholar
  29. [29]
    K.K.H. Toh, A.R. Neureuther and E.W. Scheckler, “Three-Dimensional Simulation of Optical Lithography,” SPIE Vol. 1463, pp. 356–367, March, 1991.CrossRefGoogle Scholar
  30. [30]
    K. Lee, Y. Kim and C. Hwang, “New Three-Dimensional Modeling of Optical Lithography for Positive Photoresists,” 1991 International Workshop on VLSI Process and Device Modeling, pp. 44–45, Oiso, Japan. may 26–27, 1991.Google Scholar
  31. [31]
    M. Komatsu, “Three Dimensional Resist profile Simulation,” SPIE optical/ Laser Microlithography VI, vol. 1927, pp. 413–426, 1993.MathSciNetGoogle Scholar
  32. [32]
    M. Fujinaga, N. Kotani, M. Shirahata, H. Genjo, T. Katayama, T. Ogawa, Y. Akasaka, “Three Dimensional Topography Simulation Model Using Diffusion Equation,” IEDM Technical Digest, pp. 332–335, Dec. 1988.Google Scholar
  33. [33]
    J. McVittie, J. Rey, L-.Y. Cheng, M.M. IslamRaja, and K.C. Saraswat, “LPCVD Profile Simulation Using a Re-Emission Model,” IEDM Technical Digest, pp. 917–920, December 1990.Google Scholar
  34. [34]
    J. Pelka, “Simulation of Ion-Enhanced Dry-Etch Processes,” Microelectronics Engineering, vol. 13, pp. 487–491, 1991.CrossRefGoogle Scholar
  35. [35]
    T.S. Cale, T.H. Gandy, M.K. Jain, M. Ramaswami, and G.B. Raupp, “A General Model for PVD Deposition,” Proceedings Eighth International VLSI Multilevel interconnect Conference, pp. 350–352, Santa Clara, June 11–12, 1991.Google Scholar
  36. [36]
    T. Smy, R.N. Tait, K.L. Westra, M.J. Brett “Simulation of Density Variation and Step Coverage for Via Metallization,” Proceedings IEEE V-MIC, “Santa Clara, CA, pp. 292, June 1989.Google Scholar
  37. [37]
    K.H. Toh and A.R. Neureuther, “Identifying and Monitoring Effects of Lens Aberrations in Projection Printing,” SPIE Proceedings, Vol. 772, pp. 202–209, 1987.Google Scholar
  38. [38]
    K.K.H. Toh, A.R. Neureuther and E.W. Scheckler. Neureuther and E.W.Scheckler, “Algorithms for Simulation of Three-Dimensional Etching,” IEEE Trans. CAD, Vol. CAD-13, No 5, pp. 616–624, May 1994.Google Scholar
  39. [39]
    E.W. Scheckler, N.N. Tam, A.K. Pfau and A.R. Neureuther, “An Efficient Volume Removal Algorithm for Three-Dimensional Lithography Simulation with Experimental Verification,” IEEE Trans. CAD, Vol. CAD-12, No. 9, pp. 1345–1356, Sept. 1993.Google Scholar
  40. [40]
    E.W. Scheckler and A.R. Neureuther “Models and Algorithms for Three-Dimensional Simulation with SAMPLE-3D,” IEEE Trans. CAD, Vol. CAD-13, No. 2, pp. 219–230, Feb 1994.Google Scholar
  41. [41]
    J.J. Heimsen, E.W. Scheckler, A.R. Neureuther and C.H. Sequin “An Efficient Loop Detection and Removal Algorithm for 3-D Surface-Based Lithography Simulation, ” NUPAD-IV Technical Digest, pp. 3–8, 1992.Google Scholar
  42. [42]
    U. Heimsen, “A Comparison of Three Dimensional Photolithography Simulators,” Ph.D. Thesis, University of California, Berkeley, December 1994, and ERL memorandum No. UCB/ERL M95/25 April, 1995.Google Scholar
  43. [43]
    John H. Sefler and Andrew R. Neureuther, “Extracting Solid Conductors from a Single Triangulated Surface Representation for Interconnect Analysis,” Submitted to IEEE Trans. Semiconductor Manufacturing, 1995.Google Scholar
  44. [44]
    R.H. Wang, A. Gabara, A.R. Neureuther, “BTU-Berkeley Topography Utilities for Linking Topography and Impurity Profile Simulations,” NUPADIV, Seattle, WA, pp. 225–230, May 1992.Google Scholar
  45. [45]
    Wang, M.S. Karasick, and A.R. Neureuther, “Computational Evaluation of Three-Dimensional Topography Process Simulation Components,” International Workshop on VLSI Process and Device Modeling (VPAD), Kyoto, Japan, May 1993, pp. 95–96.Google Scholar
  46. [46]
    Wang, and A.R. Neureuther, “Efficient and Innovative Use of Three-Dimensional Geometry Services in IC Topography Simulation,” International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, ROC, June 1995.Google Scholar
  47. [47]
    K. Nabors, and J. White, “FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program,” IEEE Trans. on Computer Aided Design, vol. 10, no. 11, pp. 1447–1459, Nov. 1991.CrossRefGoogle Scholar
  48. [48]
    M. Kamon, M.J. Tsuj, and J. White, “FastHenry, A multipole-Accelerated 3D Inductance Extraction program,” Proceedings of the ACM/IEEE Design Automation Conference, Dallas, June 1993.Google Scholar
  49. [49]
    M. Karasick and D. Lieber, ACM Symp. On CAD and Foundations of Geom. Modeling, pp. 15–25, June 1991.Google Scholar
  50. [50]
    J. Sethian, “Analysis of Flame Propagation,” Ph.D. Dissertation, University of California at Berkeley, 1982.Google Scholar
  51. [51]
    J. Sethian, “Numerical Algorithms for Propagating Interfaces: Hamilton-Jacobi Equations and Conservation Laws,” Journal of Differential Geometry, pp. 131–1161, 1990.Google Scholar
  52. [52]
    S. Hamaguchi, M. Dalvie, R.T. Farouki, and S. Sethuraman, “A Shock-Tracking Algorithm for Surface Evolution under Reactive-Ion Etching,” IBM Research Report, RC18283Google Scholar

Copyright information

© Springer-Verlag/Wien 1995

Authors and Affiliations

  • A. R. Neureuther
    • 1
  • R. H. Wang
    • 1
  • J. J Helmsen
    • 1
  • J. F. Sefler
    • 1
  • E. W. Scheckler
    • 1
  • R. Gunturi
    • 1
  • Rex Winterbottom
    • 1
  1. 1.Dept. of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

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