Modeling the trapping and de-trapping of phosphorus at the Si to SiO2 interface
The phosphorus dose loss by trapping at the Si-SiO2 interface was studied for the various process modules of a 0.3 µm CMOS technology, both separately and in combination. SIMS measurements showed significant dose loss, up to 30%, and also a sizable de-trapping after a 1000°C anneal. The de-trapping was observed as an additional peak at the silicon surface. A new model which includes both trapping and de-trapping phosphorus fluxes was incorporated into the process simulator PROPHET. Subsequently, simulations were able to reproduce the SIMS data as well as NMOS threshold voltage values. The model also showed that the dose loss is enhanced by TED, thereby explaining the measured dependence of the dose loss on the implanted dose, and the fact that the major dose loss in the CMOS process occurred during the first anneal after implantation.
KeywordsRapid Thermal Anneal CMOS Technology Gate Oxidation Doping Profile Furnace Anneal
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