Advertisement

Modeling the trapping and de-trapping of phosphorus at the Si to SiO2 interface

  • H.-H. Vuong
  • C. S. Rafferty
  • J. Ning
  • J. R. McMacken
  • J. McKinley
  • F. A. Stevie
Conference paper

Abstract

The phosphorus dose loss by trapping at the Si-SiO2 interface was studied for the various process modules of a 0.3 µm CMOS technology, both separately and in combination. SIMS measurements showed significant dose loss, up to 30%, and also a sizable de-trapping after a 1000°C anneal. The de-trapping was observed as an additional peak at the silicon surface. A new model which includes both trapping and de-trapping phosphorus fluxes was incorporated into the process simulator PROPHET. Subsequently, simulations were able to reproduce the SIMS data as well as NMOS threshold voltage values. The model also showed that the dose loss is enhanced by TED, thereby explaining the measured dependence of the dose loss on the implanted dose, and the fact that the major dose loss in the CMOS process occurred during the first anneal after implantation.

Keywords

Rapid Thermal Anneal CMOS Technology Gate Oxidation Doping Profile Furnace Anneal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    P. B. Griffin, S. W. Crowder, and J. M. Knight, “Dose loss in phosphorus implants due to transient enhanced diffusion and interface segregation”. Appl. Phys. Lett., vol. 67, pp. 482 – 484 (1995)CrossRefGoogle Scholar
  2. [2]
    F. Lau, L. Mader, C. Mazure, Ch. Werner, and M. Orlowski, “A model for phosphorus segregation at the silicon-silicon dioxide interface”, Appl. Phys. A., vol 49, p. 671 (1989)CrossRefGoogle Scholar
  3. 3.
    Y. Sato, M. Watanabe, and K. Imai,“Characterization of Phosphorus Pile-up at the SiO2/Si interface”, J. of Electrochem. Soc., vol. 140, pp. 2679–2682(1993).CrossRefGoogle Scholar
  4. [4]
    E. H. Nicollian and A. Chatterjee, J. Electrochem. Soc., vol. 141, p. 2182 (1994)CrossRefGoogle Scholar
  5. [5]
    H.-H. Vuong, C. S. Rafferty, J. R. McMacken, J. Ning, and S. Chaudhry, SISPAD 1997, p. 85 (1997)Google Scholar
  6. [6]
    C. S. Rafferty, H.-H. Vuong, S. A. Eshraghi, J. L. Lentz, P. M. Zeitzoff, M. R. Pinto, and S. J. Hillenius, “anomalous short-channel threshold voltage due to transient-enhanced diffusion”, IEDM 1993, pp. 311 – 314 (1993)Google Scholar
  7. [7]
    M. D. Giles, “Transient phosphorus diffusion below the amorphization threshold”, J. Electrochem. Soc., vol. 138, pp. 1160 – 1165 (1991)CrossRefGoogle Scholar
  8. [8]
    G. Hobler, priv. communication (1998)Google Scholar
  9. [9]
    F. A. Stevie et al, to be published in Proc. SIMS XI (1997)Google Scholar
  10. [10]
    S. A. Schwarz, R. W. Barton, C. P. Ho, and C. R. Helms, “Studies of Phosphorus Pile-Up at the Si-SiO2 interface using Auger Sputter profiling”, J. Electrochem. Soc., Vol. 128, p. 1101 (1981)CrossRefGoogle Scholar
  11. [11]
    H.-H. Vuong, C. S. Rafferty, S. A. Eshraghi, J. L. Lentz, P. M. Zeitzoff, M. R. Pinto, and S. J. Hillenius, “Effects of oxide interface traps and Transient Enhanced Diffusion on the process modeling of PMOS devices”, IEEE Trans. Elec. Dev., vol. 43, pp. 1144 – 1152 (1996)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1998

Authors and Affiliations

  • H.-H. Vuong
    • 1
  • C. S. Rafferty
    • 1
  • J. Ning
    • 2
  • J. R. McMacken
    • 2
  • J. McKinley
    • 3
  • F. A. Stevie
    • 3
  1. 1.Bell LaboratoriesLucent TechnologiesMurray HillUSA
  2. 2.Bell LaboratoriesLucent TechnologiesOrlandoUSA
  3. 3.Lucent TechnologiesOrlandoUSA

Personalised recommendations