Abstract
This paper outlines the capabilities of 2D process and device simulation in the development of byte-eraseable EEPROMs within a 0.35µm CMOS process. Evaluation of different cell options, investigation of critical design rules and process development have been successfully undertaken. Simulation has been shown to provide useful insight and understanding that cannot be obtained from measurements alone and can increase the speed of the design cycle.
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References
R. Duffy, “Numerical Simulation of Non-Volatile Memory Technology,” M. Eng. Sc.thesis, National University of Ireland, 1996
A. Kolodny et al, “Analysis and Modeling of Floating-Gate EEPROM Cells,” IEEE Trans. El. Dev vol. ED-33, pp. 835–844, 1986
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© 1998 Springer-Verlag/Wien
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Duffy, R., Concannon, A., Mathewson, A., de Graaf, C., Slotboom, M., Verhaar, R. (1998). Simulation based development of EEPROM devices within a 0.35µm process. In: De Meyer, K., Biesemans, S. (eds) Simulation of Semiconductor Processes and Devices 1998. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6827-1_93
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DOI: https://doi.org/10.1007/978-3-7091-6827-1_93
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7415-9
Online ISBN: 978-3-7091-6827-1
eBook Packages: Springer Book Archive