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Simulation based development of EEPROM devices within a 0.35µm process

  • R. Duffy
  • A. Concannon
  • A. Mathewson
  • C. de Graaf
  • M. Slotboom
  • R. Verhaar
Conference paper

Abstract

This paper outlines the capabilities of 2D process and device simulation in the development of byte-eraseable EEPROMs within a 0.35µm CMOS process. Evaluation of different cell options, investigation of critical design rules and process development have been successfully undertaken. Simulation has been shown to provide useful insight and understanding that cannot be obtained from measurements alone and can increase the speed of the design cycle.

Keywords

Depletion Region Tunnel Current CMOS Process Floating Gate Fast Programming 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. Duffy, “Numerical Simulation of Non-Volatile Memory Technology,” M. Eng. Sc.thesis, National University of Ireland, 1996Google Scholar
  2. [2]
    A. Kolodny et al, “Analysis and Modeling of Floating-Gate EEPROM Cells,” IEEE Trans. El. Dev vol. ED-33, pp. 835–844, 1986CrossRefGoogle Scholar

Copyright information

© Springer-Verlag/Wien 1998

Authors and Affiliations

  • R. Duffy
    • 1
  • A. Concannon
    • 1
  • A. Mathewson
    • 1
  • C. de Graaf
    • 2
  • M. Slotboom
    • 2
  • R. Verhaar
    • 2
  1. 1.National Microelectronics Research CentreLee Maltings, Prospect RowCorkIreland
  2. 2.Philips Research LaboratoriesEindhovenThe Netherlands

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