Simulation based development of EEPROM devices within a 0.35µm process
This paper outlines the capabilities of 2D process and device simulation in the development of byte-eraseable EEPROMs within a 0.35µm CMOS process. Evaluation of different cell options, investigation of critical design rules and process development have been successfully undertaken. Simulation has been shown to provide useful insight and understanding that cannot be obtained from measurements alone and can increase the speed of the design cycle.
KeywordsDepletion Region Tunnel Current CMOS Process Floating Gate Fast Programming
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