Design Optimization of RF Power MOSFET’s Using Large Signal Analysis Device Simulation of Matching Networks
This paper discusses the modeling and simulation of power MOSFET’s using large signal device simulation. In order to provide an accurate representation of an LDMOS MOSFET, a model for the intrinsic device and the extrinsic parasitic components is developed. The RF performance of the model is then verified with experimental data. With the proven model, the effect of parasitic components is analyzed and the matching networks are optimized for the desired response.
KeywordsReflection Coefficient Power Amplifier Device Simulation Match Network Power MOSFET
Unable to display preview. Download preview PDF.
- G. Ma, W. Burger, C. Dragon, and T. Gillenwater. “High Efficiency LDMOS Power FET for Low Voltage Wireless Communications”. Proceedings of IEDM. San Francisco, CA: December 1996Google Scholar
- A. Wood, C. Dragon, and W. Burger. “High Performance Silicon LDMOS Technology for 2GHz RF Power Amplifier Applications”. Proceeding of IEDM. San Francisco, CA: December 1996Google Scholar
- B. Troyanovsky, F. Rotella, Z. Yu, R. Dutton, and J. Sato-Iwanga. “Large Signal Analysis of RF/ Microwave Devices with Parasitics Using Harmonic Balance Device Simulation”. SASIMI. Fukuoka, Japan: Nov. 1996Google Scholar
- J. Cusak, S. Perlow, and B. Perlman. “Automatic Load Contour Mapping for Microwave Power Transistors”. Trans, on Microwave Theory and Techniques. Vol. MTT-22, No. 12, December 1974Google Scholar