Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer
This paper presents a novel technique to eliminate non-simultaneous triggering effects in finger-type ESD protection transistor using SiGe heterojunction buried layer structures. It is confirmed that lower snapback voltage and maximum lattice temperature are obtainable in the new structure based on device simulation. As a result, current localization and lattice overheating of a finger-type protection transistor caused by process variations can be avoided in this structure.
KeywordsCurrent Gain NMOS Transistor SiGe Layer Uniform Current Distribution Thin Gate Oxide
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