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Layout-Based 3D Solid Modeling of IC Structures and Interconnects Including Electrical Parameter Extraction

  • Xiaoning Qi
  • Sherry Y. Shen
  • Ze-Kai Hsiau
  • Zhiping Yu
  • Robert Dutton
Conference paper

Abstract

A suite of software tools have been developed to model IC structures including interconnects based on layout design and processing information. The modeling capabilities include 3D rendering of solid objects, surface meshing, electrical parameter (mainly capacitance) extraction for arbitrarily shaped objects. This software ensemble provides a direct link between design parameters and electrical performance. Analysis of a four transistor SRAM cell is used as an example.

Keywords

Boundary Element Method Surface Meshing Layout Design SRAM Cell Polysilicon Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Xe-Kai Hsiau, et al. “Robust, Stable, and Accurate Boundary Movement for Physical Etching and Deposition Simulation”, IEEE Transactions on Electron Devices, Vol. 44, No. 9, September 1997Google Scholar
  2. [2]
    Zhiping Yu, “Layout Based 3D Geometric Modeling for IC”, Proceedings of International Symposium on VLSI Technology., System and Applications, pp. 108–112, June 1995Google Scholar
  3. [3]
    K. Nabors, et al., “Fast Capacitance Extraction of General Three-Dimension Structure”, IEEE Transactions on Micro wave Theory and Techniques, Vol. 40, No. 7, pp. 1496–1506 July, 1992CrossRefGoogle Scholar
  4. [4]
    R.W. Dutton, et al. “Device Simulation for RF Applications”, IEDM’97, invited paper, 1997Google Scholar

Copyright information

© Springer-Verlag/Wien 1998

Authors and Affiliations

  • Xiaoning Qi
    • 1
  • Sherry Y. Shen
    • 1
  • Ze-Kai Hsiau
    • 1
  • Zhiping Yu
    • 1
  • Robert Dutton
    • 1
  1. 1.Center for Integrated SystemsStanford UniversityStanfordUSA

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