A Newly Proposed Delay Improvement on CMOS/SOI Future Technology
Contribution of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep sub-micrometer gate is propounded. Measurements of the fifty-one stage ring oscillator’s time delay are completed for comparison with analytical model. Propagation Delay Times(TPD) by reducing Poly-Si gate thickness were improved up to two times in deep-submicron CMOS/SIMOX inverters. It is concluded that SOI technology is promising for a. high speed by reducing gate fringing capacitance which is correlated to the poly-Si gate thickness.
KeywordsGate Length Future Technology Capacitance Model Gate Width Gate Capacitance
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- T. Douseki K. Aoyama and Y. Omura, “Dependence of CMOS/SIMOX inverter delay time on gate overlap capacitance,” IEICE Trans., ED92–62(176):39–44, Aug. 1992Google Scholar
- M. Fujishima, M. Ikeda, K. Asada, Y. Omura and K. Izumi, “Analytical Modeling of Dynamic Performance of Deep Sub-micron SOI/SIMOX based on Current-Delay Product,” IEICE Trans. Electron., E75-C(12):1506–1514, Dec. 1992Google Scholar
- M. Lee and R. Asada, “Deep Sub-micron CMOS/SIMOX delay modeling by Time-Dependent Capacitance Model,” IEEE Trans. on Electron Devices, To be published, July, 1993Google Scholar
- M. Lee and K. Asada, “Sub-100nm CMOS/SIMOX Delay Modeling by Time-Dependent Gate Capacitance Model,” 1993 International Symposium on VLSI TSA,Presented, Taipei, Taiwan, May 1993Google Scholar
- S. R. Vemuru and A. R. Thorbjornsen, “A MODEL FOR. DELAY EVALUATION OF A CMOS INVERTER,” 1990 IEEE Int. Sym. on CAS,ISCAS-90(1):89–92, May. 1990Google Scholar