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A Newly Proposed Delay Improvement on CMOS/SOI Future Technology

  • M. Lee
  • K. Asada
Conference paper

Abstract

Contribution of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep sub-micrometer gate is propounded. Measurements of the fifty-one stage ring oscillator’s time delay are completed for comparison with analytical model. Propagation Delay Times(TPD) by reducing Poly-Si gate thickness were improved up to two times in deep-submicron CMOS/SIMOX inverters. It is concluded that SOI technology is promising for a. high speed by reducing gate fringing capacitance which is correlated to the poly-Si gate thickness.

Keywords

Gate Length Future Technology Capacitance Model Gate Width Gate Capacitance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • M. Lee
    • 1
    • 2
  • K. Asada
    • 1
  1. 1.Department of Electronic EngineeringThe University of TokyoTokyoJapan
  2. 2.Nippon Motorola LtdTokyoJapan

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