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Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

  • W. Kuźmicz
  • W. Denisiuk
  • J. Gempel
  • Z. Jaworski
  • M. Niewczas
  • A. Pfitzner
  • E. Piwowarska
  • W. Pleskazc
  • A. Wojtasik

Abstract

This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a process/device simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented.

Keywords

Spatial Dependency Device Modeling Circuit Simulation Input Stage Device Simulator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • W. Kuźmicz
    • 1
  • W. Denisiuk
    • 1
  • J. Gempel
    • 1
  • Z. Jaworski
    • 1
  • M. Niewczas
    • 1
  • A. Pfitzner
    • 1
  • E. Piwowarska
    • 1
  • W. Pleskazc
    • 1
  • A. Wojtasik
    • 1
  1. 1.Institute for Microelectronics and OptoelectronicsWarsaw University of TechnologyWarszawaPoland

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