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Analysis of a CMOS-Compatible Vertical Bipolar Transistor

  • G. Schrom
  • S. Selberherr
  • F. Unterleitner
  • J. Trontelj
  • V. Kunc
Conference paper

Abstract

A vertical npn bipolar transistor (BJT) which can be manufactured in a simple p-well CMOS process without additional process steps is described. The proposed BJT uses a p-well as base and an n + S/D doping as emitter. The collector consists of the n -substrate and does not require an n + buried layer or a highly doped substrate. The device is especially suitable for high-voltage applications in electrically hostile environments such as automotive circuits.

Keywords

CMOS Process Junction Depth Base Contact Dope Substrate Protection Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    W. Kausel, G. Nanz, S. Selberherr, H. Pötzl, BAMBI — A transient two-dimensional device simulator using implicit backward Euler’s method and a totally self-adaptive grid, NUPAD II Workshop, May 9–10, 1988, San Diego, Ca., Digest No. 105/106.Google Scholar
  2. [2]
    F. Berta, J. Fernandez et al., A Simplified Low-Voltage Smart Power Technology, IEEE Electron Device Lett., pp. 465–467, 1991.Google Scholar

Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • G. Schrom
    • 1
  • S. Selberherr
    • 1
  • F. Unterleitner
    • 2
  • J. Trontelj
    • 3
  • V. Kunc
    • 3
  1. 1.Institute for MicroelectronicsTU ViennaWienAustria
  2. 2.Austria Mikro Systeme GmbH SchloßPremstättenUnterpremstättenAustria
  3. 3.Laboratory for MicroelectronicsUniversity of LjubljanaLjubljanaSlovenia

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