Hot Carrier Suppression for an Optimized 10V CMOS Process

  • A. Bauer
  • H. Noll
  • H. Pimingstorfer
Conference paper


An advanced 2µm twin-well CMOS process for mixed analog/digital designs with operating voltages up to 10 Volts is presented. The process uses an optimized LDD-structure with high-energy n-implant for the n-channel transistors which drastically reduces the substrate current by a factor of approximately 50 compared to a standard 2µm/5V process technology. A number of relevant process parameters have been optimized to find the ideal balance between driving capability/speed and long-time reliability.


Gate Voltage Drain Current Substrate Current High Operating Voltage Relevant Process Parameter 
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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • A. Bauer
    • 1
  • H. Noll
    • 1
  • H. Pimingstorfer
    • 2
  1. 1.Reasearch and DevelopmentAMS Austria Mikro Systeme International AG Schloß PremstättenUnterpremstättenAustria
  2. 2.Institute for MicroelectronicsTU ViennaWienAustria

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