Advertisement

Process Flow Representation within the VISTA Framework

  • Ch. Pichler
  • S. Selberherr

Abstract

The execution of multi-step simulation sequences involving a number of independent simulation tools is taken care of by the VISTA simulation flow control module which allows for the definition of a simulation task by means of the simulation flow description, a representation of the process flow using symbolic names to call simulation tools. Large process flows can be modeled by using predefined sequences, where the calculation results of all intermediate simulation steps remain available for analysis at a later time. Data level integration is based on the PIF data exchange format which is used to create a wafer state description containing all wafer geometry and material data after each simulation step.

Keywords

Simulation Tool Simulation Step Simulation Sequence Simulation Task Predefined Sequence 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    D. S. Boning, Semiconductor Process Design: Representations, Tools, and Methodologies, PhD Thesis, Massachusetts Institute of Technology, January 1991.Google Scholar
  2. [2]
    A. S. Wong, Technology Computer-Aided Design Frameworks and the PROSE Implementation, PhD Thesis, University of California, Berkeley, 1992.Google Scholar
  3. [3]
    E. W. Scheckler et al., A Utility-Based Integrated System for Process Simulation, IEEE Trans. Comp. Aided Design, Vol. 11, No. 7, pp. 911–920, 1992.CrossRefGoogle Scholar
  4. [4]
    H. Pimingstorfer et al., A Technology CAD Shell, SISDEP IV, pp. 409–416, 1991.Google Scholar
  5. [5]
    S. Halama et al., Consistent User Interface and Task Level Architecture of a TCAD System, NUPAD IV, pp. 237–242, 1992.Google Scholar
  6. [6]
    G. Hobler et al., RTA-Simulation with the 2D Process Simulator PROMIS, NU-PAD III, pp. 13–14, 1990Google Scholar
  7. [7]
    W. G. Oldham et al., A General Simulator for VLSI Lithography and Etching Processes: Part II-Application to Deposition and Etching, IEEE Trans. Electron Devices, Vol. ED-27, No. 8, pp. 1455–1459, 1980.CrossRefGoogle Scholar
  8. [8]
    St. G. Duvall, An Interchange Format for Process and Device Simulation, IEEE Trans. Comp. Aided Design, Vol. 7 No. 7 pp. 741–754, 1988.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • Ch. Pichler
    • 1
  • S. Selberherr
    • 1
  1. 1.Institute for MicroelectronicsTU ViennaWienAustria

Personalised recommendations