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Applied TCAD in Mega-Bits Memory Design

  • H. Masuda
  • H. Pimingstorfer
  • H. Sato
  • K. Tsuneno
  • K. Ichikawa
  • H. Tobe
  • H. Miyazawa
  • M. Nakamura
  • K. Kajigaya
  • O. Tsuchiya
  • T. Matsumoto
Conference paper

Abstract

This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based circuit model parameter generation for chip design purpose is one of the key topics in TCAD. Several critical phenomena, such as CMOS latchup etc., were also analyzed to verify feasibility and performance of the memory process. Two months of TCAD analysis were required, in which twelve sets of MOS model parameters were generated by VISTA with the computational cost of six hours on six CPUs of SGI-IRIS machines.

Keywords

Critical Phenomenon Drain Current Versus Data Parameter Extraction Soft Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • H. Masuda
    • 1
  • H. Pimingstorfer
    • 2
  • H. Sato
    • 1
  • K. Tsuneno
    • 1
  • K. Ichikawa
    • 1
  • H. Tobe
    • 1
  • H. Miyazawa
    • 1
  • M. Nakamura
    • 1
  • K. Kajigaya
    • 1
  • O. Tsuchiya
    • 1
  • T. Matsumoto
    • 1
  1. 1.Hitachi, LtdImai, Ome-shiJapan
  2. 2.Institute for MicroelectronicsTU ViennaWienAustria

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