Practical Use of a Hierarchical Linear Solver Concept for 3D MOS Device Simulation
Three-dimensional device simulations of sidewall trench-isolated MOSFETs involve linear systems of equations that are extremely ill-conditioned if the geometric channel length exceeds 2µm. Since conventional preconditioned iterative methods tend to fail in such cases we have implemented a robust iterative linear solver using a hierarchy of incomplete factorizations of the coefficient matrix.
KeywordsIteration Count Matrix Entry Sparsity Pattern Incomplete Factor Semiconductor Device Simulator
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