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Practical Use of a Hierarchical Linear Solver Concept for 3D MOS Device Simulation

  • O. Heinreichsberger
  • M. Thurner
  • S. Selberherr

Abstract

Three-dimensional device simulations of sidewall trench-isolated MOSFETs involve linear systems of equations that are extremely ill-conditioned if the geometric channel length exceeds 2µm. Since conventional preconditioned iterative methods tend to fail in such cases we have implemented a robust iterative linear solver using a hierarchy of incomplete factorizations of the coefficient matrix.

Keywords

Iteration Count Matrix Entry Sparsity Pattern Incomplete Factor Semiconductor Device Simulator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • O. Heinreichsberger
    • 1
  • M. Thurner
    • 2
  • S. Selberherr
    • 1
  1. 1.Institute for MicroelectronicsTU ViennaWienAustria
  2. 2.Campus Based Engineering Center ViennaDigital Equipment CorporationWienAustria

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