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Practical Use of a Hierarchical Linear Solver Concept for 3D MOS Device Simulation

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Simulation of Semiconductor Devices and Processes

Abstract

Three-dimensional device simulations of sidewall trench-isolated MOSFETs involve linear systems of equations that are extremely ill-conditioned if the geometric channel length exceeds 2µm. Since conventional preconditioned iterative methods tend to fail in such cases we have implemented a robust iterative linear solver using a hierarchy of incomplete factorizations of the coefficient matrix.

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References

  1. M. Driessen, H.A.v.d. Vorst, Bi-CGSTAB in Semiconductor Modeling, Proc. SISDEP (1991).

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Author information

Authors and Affiliations

  1. Institute for Microelectronics, TU Vienna, Gußhausstraße 27-29, A-1040, Wien, Austria

    O. Heinreichsberger & S. Selberherr

  2. Campus Based Engineering Center Vienna, Digital Equipment Corporation, Favoritenstraße 7, A-1040, Wien, Austria

    M. Thurner

Authors
  1. O. Heinreichsberger
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  2. M. Thurner
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  3. S. Selberherr
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Editor information

Editors and Affiliations

  1. Institut für Mikroelektronik, Technische Universität Wien, Austria

    Siegfried Selberherr , Hannes Stippel  & Ernst Strasser ,  & 

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© 1993 Springer-Verlag Wien

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Heinreichsberger, O., Thurner, M., Selberherr, S. (1993). Practical Use of a Hierarchical Linear Solver Concept for 3D MOS Device Simulation. In: Selberherr, S., Stippel, H., Strasser, E. (eds) Simulation of Semiconductor Devices and Processes. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6657-4_20

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  • DOI: https://doi.org/10.1007/978-3-7091-6657-4_20

  • Publisher Name: Springer, Vienna

  • Print ISBN: 978-3-7091-7372-5

  • Online ISBN: 978-3-7091-6657-4

  • eBook Packages: Springer Book Archive

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