Scaling of Conventional MOSFET’s to the 0.1-µm Regime
As fundamental limits of MOSFET’s are being explored, new device structures have been proposed in order to maintain good short-channel behaviour in the deep submicron regime. These advanced transistors usually require complex channel and source/drain engineering, and will probably not be excepted by industry if the conventional way of scaling is still feasible. The conventional MOSFET is the benchmark for semiconductor industries. This paper addresses some of the issues which are important when conventional MOSFET’s are scaled down to the deep submicron regime.
KeywordsThreshold Voltage Design Rule Inversion Layer Power Supply Voltage Junction Depth
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- 4]J. Slotboom, et al., “Non-Local Impact Ionization in Silicon Devices”, Tech. Digest IEDM, p. 127 (1991).Google Scholar
- 5]J. Slotboom, G. Streutker, G. Davids, and P. Hartog, “Surface Impact Ionization in Silicon Devices”, Tech. Digest IEDM, p. 494 (1987).Google Scholar
- 7]P. Woerlee et al., “The Impact on Hot-Carrier Degradation and Supply Voltage of Deep-Submicron NMOS Transistors”, Tech. Digest IEDM, p. 537 (1991).Google Scholar
- 8]F. Stern, “Quantum properties of surface space-charge layers”, CRC Crit. Rev. Solid State Sci., p. 499, 1974.Google Scholar
- 9]M. van Dort et al, “Quantum-Mechanical Threshold Voltage Shifts of MOSFET’s Caused by High Levels of Channel Doping”, Tech. Digest IEDM, p. 495 (1991).Google Scholar
- 13]H. Noda, F. Murai, and S. Kimura, “Threshold Voltage Controlled 0.1-µm MOSFET Utilizing Inversion Layer as Extreme Shallow Source/Drain”, Tech. Digest IEDM, p. 123 (1993).Google Scholar
- 14]M. Orlowski, C. Mazuré and F. Lau, “Submicron Short Channel Effects due to Gate Reoxidation Induced Lateral Interstitial Diffusion”, Techn. Digest IEDM, p. 632 (1987).Google Scholar
- 15]C. Rafferty et al., “Explanation of Reverse Short Channel Effect by Defect Gradients”, Tech.Dig. IEDM, p. 311, 1993.Google Scholar
- 16]M. van Dort et al., “Two-Dimensional Transient-Enhanced Diffusion and Its Impact on Bipolar Transistors”, Tech. Dig. IEDM, p 865, 1994.Google Scholar
- 17]A. Hori et al., “A 0.05-µm with Ultra Shallow S/D Junctions Fabricated by 5 keV Ion Implantation an Rapid Thermal Annealing”, Tech.Dig. IEDM, p. 485 (1994).Google Scholar
- 18]M. van Dort and D. Klaassen, “Sensitivity Analysis of an Industrial CMOS Process using RSM Techniques”, Proc. SISPAD, 1995.Google Scholar