Abstract
As fundamental limits of MOSFET’s are being explored, new device structures have been proposed in order to maintain good short-channel behaviour in the deep submicron regime. These advanced transistors usually require complex channel and source/drain engineering, and will probably not be excepted by industry if the conventional way of scaling is still feasible. The conventional MOSFET is the benchmark for semiconductor industries. This paper addresses some of the issues which are important when conventional MOSFET’s are scaled down to the deep submicron regime.
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© 1995 Springer-Verlag Wien
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van Dort, M.J., Slotboom, J.W., Woerlee, P.H. (1995). Scaling of Conventional MOSFET’s to the 0.1-µm Regime. In: Ryssel, H., Pichler, P. (eds) Simulation of Semiconductor Devices and Processes. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6619-2_91
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DOI: https://doi.org/10.1007/978-3-7091-6619-2_91
Publisher Name: Springer, Vienna
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