Ultra High Performance, Low Power 0.2 µm CMOS Microprocessor Technology and TCAD Requirements

  • A. Nasr
  • J. Faricelli
  • N. Khalil
  • C.-L. Huang


The process requirements for low power, ultra high performance CMOS Digital IC’s are reviewed. The role, accuracy, and demands of TCAD for future process and device design are discussed. In addition, special challenges for predictive simulation of process and device behavior are highlighted. Two illustrative examples are presented. First, the interaction between the polysilicon gate process architecture and the resulting device characteristics is analyzed in details. Second, subthreshold leakage current (Id off) prediction for devices with 0.2 µm length and below is addressed. A TCAD based inverse modeling strategy is proposed to enhance the predictability of sub-quarter micron CMOS device behavior.


Gate Length Doping Profile Gate Capacitance Short Channel Effect Gate Oxide Thickness 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Wien 1995

Authors and Affiliations

  • A. Nasr
    • 1
  • J. Faricelli
    • 1
  • N. Khalil
    • 1
  • C.-L. Huang
    • 1
  1. 1.Ultra Large Scale Integration Operations GroupDigital SemiconductorHudsonUSA

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