Layout Design Rule Generation with TCAD Tools for Manufacturing

  • José López-Serrano
  • Andrzej J. Strojwas
Conference paper


This paper presents a methodology for estimating the effects of changes in the layout design rules on the manufacturability of a VLSI technology. 2-D process and device simulations were used to estimate parametric yield, while functional yield was predicted with state-of-theart yield modeling tools. A spectrum of TCAD tools was therefore capable of estimating the resulting number of good chips per wafer for different sets of VLSI layout design rules.


Parametric Yield Design Rule PMOS Transistor Chip Size Functional Yield 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Wien 1995

Authors and Affiliations

  • José López-Serrano
    • 1
  • Andrzej J. Strojwas
    • 1
  1. 1.Electrical and Computer Engineering DepartmentCarnegie Mellon UniversityPittsburghUSA

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