Layout Design Rule Generation with TCAD Tools for Manufacturing
This paper presents a methodology for estimating the effects of changes in the layout design rules on the manufacturability of a VLSI technology. 2-D process and device simulations were used to estimate parametric yield, while functional yield was predicted with state-of-theart yield modeling tools. A spectrum of TCAD tools was therefore capable of estimating the resulting number of good chips per wafer for different sets of VLSI layout design rules.
KeywordsParametric Yield Design Rule PMOS Transistor Chip Size Functional Yield
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