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Process- and Devicesimulation of Very High Speed Vertical MOS Transistors

  • F. Lau
  • W. H. Krautschneider
  • F. Hofmann
  • H. Gossner
  • H. Schäfer

Abstract

Optical lithography does not allow the scaling of MOS transistors down to 100nm dimensions. Thus the channel length of high speed MOS devices must depend on alternative processing steps. In this work layer deposition and etching are analysed with respect to the formation of very short MOS transistors with vertical orientation. Dopant diffusion with very steep gradients are studied in epitaxial layers. Process and device engineering aspects for a vertical MOS transistor at the sidewall of an etched trench are discussed.

Keywords

Molecular Beam Epitaxy Epitaxial Layer Channel Length Dislocation Loop Doping Profile 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    A.H. Perera et.al.; IEDM Tech. Dig. 1994, p.851Google Scholar
  2. [2]
    W.H. Krautschneider, F. Lau, H. Gossner and H. Schaefer; to be printed in Proceedings of the MRS 1994 Fall Meeting, Symposium FGoogle Scholar
  3. [3]
    Technology Modeling Associates, Palo Alto CAGoogle Scholar
  4. [4]
    K. Ghaderi et.al.; The Electrochem. Soc., Spring Meeting 1994, Ext. Abstr., No.459Google Scholar

Copyright information

© Springer-Verlag Wien 1995

Authors and Affiliations

  • F. Lau
    • 1
  • W. H. Krautschneider
    • 1
  • F. Hofmann
    • 1
  • H. Gossner
    • 1
  • H. Schäfer
    • 1
  1. 1.SIEMENS AG, Corp. R&DMunichGermany

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