Process- and Devicesimulation of Very High Speed Vertical MOS Transistors

Abstract

Optical lithography does not allow the scaling of MOS transistors down to 100nm dimensions. Thus the channel length of high speed MOS devices must depend on alternative processing steps. In this work layer deposition and etching are analysed with respect to the formation of very short MOS transistors with vertical orientation. Dopant diffusion with very steep gradients are studied in epitaxial layers. Process and device engineering aspects for a vertical MOS transistor at the sidewall of an etched trench are discussed.