On VLSI Implementation of Multiple Output Sequential Learning Networks
In this paper we propose a hardware implementation of a binary neural network architecture obtained from a new efficient constructive algorithm. This algorithm is particularly interesting because it can treat boolean as well as real valued classification problems with an arbitrary number of outputs. The networks obtained consist of binary neurons organized in two hidden layers. The first layer is implemented on a systolic architecture which represents a good tradeoff between speed and area. Due to the particular computation performed by the second hidden layer, its implementation is straightforward and well-suited to the systolic architecture. A limited number of logical gates is needed for its implementation. The output neurons are also easy to implement but require a small size memory.
KeywordsHide Layer Clock Cycle Logical Gate Hardware Implementation Output Neuron
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