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On VLSI Implementation of Multiple Output Sequential Learning Networks

  • A. Bermak
  • H. Poulard
Conference paper

Abstract

In this paper we propose a hardware implementation of a binary neural network architecture obtained from a new efficient constructive algorithm. This algorithm is particularly interesting because it can treat boolean as well as real valued classification problems with an arbitrary number of outputs. The networks obtained consist of binary neurons organized in two hidden layers. The first layer is implemented on a systolic architecture which represents a good tradeoff between speed and area. Due to the particular computation performed by the second hidden layer, its implementation is straightforward and well-suited to the systolic architecture. A limited number of logical gates is needed for its implementation. The output neurons are also easy to implement but require a small size memory.

Keywords

Hide Layer Clock Cycle Logical Gate Hardware Implementation Output Neuron 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Wien 1998

Authors and Affiliations

  • A. Bermak
    • 1
  • H. Poulard
    • 2
  1. 1.Laboratoire d’Analyse et d’Architecture des Systèmes — CNRSToulouseFrance
  2. 2.ACTIAToulouseFrance

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