TCAD Analysis of Gain Cell Retention Time for SRAM Applications
We present simulations of a recently published SRAM memory gain cell consisting of two transistors and one MOS capacitor, representing an alternative to conventional six transistor SRAMs. Inverse modeling is used to fit a given device characteristic to measurement data. To account for de-charging due to tunneling, we use a simple, non-local tunneling model and calibrate it with data from literature. By optimization, we find values for the contact voltages in the off-region at which the retention time is a maximum.
KeywordsLeakage Current Inverse Modeling Storage Node Doping Profile SRAM Cell
Unable to display preview. Download preview PDF.