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TCAD Analysis of Gain Cell Retention Time for SRAM Applications

  • A. Gehring
  • C. Heitzinger
  • T. Grasser
  • S. Selberherr
Conference paper

Abstract

We present simulations of a recently published SRAM memory gain cell consisting of two transistors and one MOS capacitor, representing an alternative to conventional six transistor SRAMs. Inverse modeling is used to fit a given device characteristic to measurement data. To account for de-charging due to tunneling, we use a simple, non-local tunneling model and calibrate it with data from literature. By optimization, we find values for the contact voltages in the off-region at which the retention time is a maximum.

Keywords

Leakage Current Inverse Modeling Storage Node Doping Profile SRAM Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Wien 2001

Authors and Affiliations

  • A. Gehring
    • 1
  • C. Heitzinger
    • 1
  • T. Grasser
    • 1
  • S. Selberherr
    • 1
  1. 1.Institute for MicroelectronicsTU Vienna

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