Advertisement

Investigations of Salicided and Salicide-Blocked MOSFETs for ESD Including ESD Simulation

  • V. Axelrad
  • Y. Huh
  • J. W. Chen
  • P. Bendix

Abstract

Standard salicided MOSFETs have been repeatedly shown to have inferior ESD protection properties in comparison to salicide-blocked MOSFETs. Standard explanations typically attribute this to shallower current flow and higher peak current density in salicided devices due to the higher conductivity of salicides. In this work we present a numerical analysis of the phenomenon using physical mixed-mode circuit-device simulation. Our results show that the inherent lack of thickness uniformity known to exist in salicide layers can lead to local concentration of current flow and thus local failure of the device.

Keywords

Breakdown Curve Inherent Lack Finger Performance Good Heat Dissipa High Peak Current Density 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    A. Palella, et al., A Design Methodology for ESD Protection Networks, EOS/ESD 1985, pp. 24–40.Google Scholar
  2. [2]
    C. Duvvury, et al., ESD Design Considerations for ULSI, EOS/ESD 1985, pp. 45–48.Google Scholar
  3. [3]
    C. Diaz, et al., Studies of EOS Susceptibility in 0.6um nMOS EOS I/O Protection Structures, EOS/ESD 1993, pp. 83–91.Google Scholar
  4. [4]
    A. Amerasekera et al., ESD Failure Modes: Characteristics, Mechanisms and Process Influences, IEEE TED-39 1992, p.2.Google Scholar
  5. [5]
    S. Beebe, Methodology for Layout Design and Optimization of ESD Protection Transistors, ESD/EOS 1996, pp. 265–275.Google Scholar
  6. [6]
    T. Polgreen, et al., Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow, IEEE TED-39, pp. 379–388.Google Scholar
  7. [7]
    K. Verhaege, et al., Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices, ESD/EOS 2000, pp. 18–28.Google Scholar
  8. [8]
    SEQUOIA Device Designer Users’ Guide, SEQUOIA Design Systems, 1998–2001Google Scholar
  9. [9]
    S. Beebe, Simulation of Complete CMOS I/O Circuit Response to CDM Stress, ESD/EOS 1998, pp. 259–270.Google Scholar
  10. [10]
    M. Mergens, et al., ESD-level Circuit Simulation - Impact of Gate RC-Delay on HBM and CDM Behavior, ESD/EOS 2000, pp. 446–155.Google Scholar

Copyright information

© Springer-Verlag Wien 2001

Authors and Affiliations

  • V. Axelrad
    • 1
  • Y. Huh
    • 1
  • J. W. Chen
    • 2
  • P. Bendix
    • 2
  1. 1.SEQUOIA Design SystemsWoodsideUSA
  2. 2.Santa ClaraLSI Logic Corp.USA

Personalised recommendations