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A Simulation Evaluation of 100nm CMOS Device Performance

  • S K Jones
  • D J Bazley
  • E Augendre
  • G Badenes
  • A K Keersgieter IMEC
  • T Skotnicki
Conference paper

Abstract

This paper presents a simulation evaluation of the performance of 100nm MOSFET devices. Calibration of 2D physical device models against measured 0.13 micron NMOS and PMOS devices forms the basis for a study of different MOSFET device options. The sensitivity of individual design factors is assessed on the device Ion/Ioff performance. The feasibility of achieving the ITRS-2000 specifications is addressed and limitations to the benefit of gate dielectric thickness scaling are identified.

Keywords

Gate Oxide Gate Length Simulation Evaluation Doping Activation PMOS Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Wien 2001

Authors and Affiliations

  • S K Jones
    • 1
  • D J Bazley
    • 1
  • E Augendre
    • 2
  • G Badenes
    • 2
  • A K Keersgieter IMEC
    • 2
  • T Skotnicki
    • 3
  1. 1.Caswell Technology, Marconi Optical ComponentsCaswell, Towcester, Northants NN12 8EQUK
  2. 2.Kapeldreef 75LeuvenBelgium
  3. 3.ST Microelectronics850 rue Jean MonnetCrollesFrance

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