A Simulation Evaluation of 100nm CMOS Device Performance
This paper presents a simulation evaluation of the performance of 100nm MOSFET devices. Calibration of 2D physical device models against measured 0.13 micron NMOS and PMOS devices forms the basis for a study of different MOSFET device options. The sensitivity of individual design factors is assessed on the device Ion/Ioff performance. The feasibility of achieving the ITRS-2000 specifications is addressed and limitations to the benefit of gate dielectric thickness scaling are identified.
KeywordsGate Oxide Gate Length Simulation Evaluation Doping Activation PMOS Device
Unable to display preview. Download preview PDF.