Tcad Driven Process Design of 0.15μm Fully-Depleted Soi Transistor for Low Power Applications
We presented a TCAD-driven total design methodology of FD-SOI MOSFETs, starting from 0.35µm/2.5V shrinking to 0.15µm/1.5V. Jumping from 0.351.1m to 0.15µm, two-phase experiments are performed effectively supported by exhaustive applications of TCAD local models. SOI specific consideration of SOI film thickness variations (oTsoi) and floating-body effects are the key points for the TCAD driven strategy.
KeywordsShort Channel Effect Response Surface Function Supply Voltage Reduction SIMOX Wafer Exhaustive Application
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