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A New Compact Spice-like Model of E2PROM Memory Cells Suitable for DC and Transient Simulations

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Abstract

This paper presents for the first time a new compact Spice-like model of a E2PROM Memory Cells suitable for both DC and transient circuit simulations. This model is based on a new Floating Gate voltage calculation procedure that improves strongly the accuracy of the modeling of the cell. Moreover, this model features many advantages compared to the previous ones: i) it is simple to implement and scale; ii) its computational time is not critical; iii) its parameter extraction procedure is the same of a MOS transistor; iv) it can be easily upgraded to take into account leakage current contributions (SILC).

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References

  1. R. Duane, A. Concannon, P. O’Sullivan, A. Mathewson (1998): Advanced numerical modelling of non-volatile memory cells. In Proceedings of the European Solid-State Device Research Conference, ESSDERC’98, Bordeaux, France. Edition Forntieres, pp. 304–307

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  2. L. Larcher, P. Pavan, F. Pellizzer, G. Ghidini (2001): A new model of gate capacitance as a simple tool to extract MOS parameters. IEEE Trans. Electron Dev. 48: 935–945

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© 2001 Springer-Verlag Wien

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Larcher, L., Pavan, P., Cuozzo, M., Marmiroli, A. (2001). A New Compact Spice-like Model of E2PROM Memory Cells Suitable for DC and Transient Simulations. In: Tsoukalas, D., Tsamis, C. (eds) Simulation of Semiconductor Processes and Devices 2001. Springer, Vienna. https://doi.org/10.1007/978-3-7091-6244-6_58

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  • DOI: https://doi.org/10.1007/978-3-7091-6244-6_58

  • Publisher Name: Springer, Vienna

  • Print ISBN: 978-3-7091-7278-0

  • Online ISBN: 978-3-7091-6244-6

  • eBook Packages: Springer Book Archive

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