An Efficient Tool for Extraction of Interconnect Models in Submicron Layouts
During these last years the width of interconnects in silicon layouts has been reduced to less than 0.25m, the number of metal levels has been increased up to five and the contributions to parasitic capacitances has become dominant. This is why a renewed interest has been triggered on the development of improved extraction methods and recent literature reports a large number of proposals. Capacitance evaluation is a well known and studied problem which requires the solution of the Laplace‘s equation for the electrostatic potential. Many codes have been developed so far, based on finite element or finite difference methods, solving the Laplace’s equation even in a 3D geometry; however they can be seldom applied to real life silicon layouts, since due to the layout geometrical complexity they easily run out of computer resources. The bottleneck is usually circumvented by avoiding the solution of Laplace‘s equation for the entire layout and trying to break the problem into many elementary geometries (sub-problems) or by not considering the real 3D geometry. Those are the so called “quasi 3D” or “2.5D” extractors. In this paper we present an alternative approach for parasitic extraction which solves the Laplace’s equation considering the entire layout without making any geometrical simplification or breaking. It is based on an extended version of the Floating Random Walk algorithm (FRW) . The use of FRW is not novel, but so far it has been limited to the extraction of the total capacitance of the interconnect. Here we show how to use FRW together with the Picard-Carson iterative procedure  in order to efficiently get a compact model of an interconnect.
KeywordsGround Plane Parasitic Capacitance Simple Cell Memory Allocation Italian National Research Council
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