Statistical Analysis of VLSI Using TCAD

  • Naoyuki Shigyo
Conference paper


Statistical process fluctuations influence upon device and circuit performance of VLSI with device miniaturization. Thus, robust process, device and circuit designs are needed. This article describes the statistical analysis of MOSFET and interconnect using Technology CAD (TCAD).


Monte Carlo Grid Size Circuit Simulation Threshold Voltage Versus Titanium Silicide 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Director, S.W., Maly, W. (Ed.) (1994): Statistical approach to VLSI. North-Holland.Google Scholar
  2. [2]
    Jones, R.E., Mele, T.C. (1991): Use of screening and response surface measuremental designs for development of a 0.5-um CMOS self-aligned titanium silicide process. IEEE Trans. Semi. Manuf., 4: 281.CrossRefGoogle Scholar
  3. [3]
    Bakoglu, H.B., Meindl, J.D. (1985): Optimum interconnection circuits for VLSI. IEEE Trans. Electron Devices, ED-32: 903.Google Scholar
  4. [4] Walker, D.M.H. et al. (1993): A TCAD framework for development and manufacturing. Technology CAD Systems (Ed. F. Fashing et al.): 83.Google Scholar
  5. [5]
    Shigyo, N., et al. (2000): Technology CAD based statistical simulation of MOSFET's. Solid-St. Electronics, 44: 1001.Google Scholar
  6. [6]
    Greenwood, J.A., Sandomire, M.M. (1950): Sample size required for estimating the standard deviation as a per cent of its true value. J. American Stat. Assoc., 45: 257.MATHCrossRefGoogle Scholar
  7. [7] pdFab version 3.1 User's Reference Manual (1997): PDF Solutions.Google Scholar
  8. [8]
    Shigyo, N. (2000): An analysis of process fluctuation induced propagation delay variation using analytical model: Solid-St. Electronics, 44: 2183.Google Scholar
  9. [9]
    Shigyo, N., Tanimoto, H., Enda, T. (2000): Mesh related problems in device simulation: Treatments of meshing noise and leakage current. Solid-St. Electronics, 44: p. 11.Google Scholar
  10. [10]
    Tanimoto, H., Shigyo, N. (1992): Discretization error in MOSFET device simulation. IEEE Trans. Computer Aided Design, 11: 921.CrossRefGoogle Scholar
  11. [11]
    Enda T., Shigyo, N. (1997): Grid size independent model of inversion layer carrier mobility. Proc. SISPAD'97: 319.Google Scholar
  12. [12]
    Watt J.T., Plummer, J.D. (1987): Universal mobility-field curve for electrons and holes in MOS inversion layers. Symp. VLSI Tech. Dig. Papers: 81.Google Scholar
  13. [13]
    Shin, H. et al. (1989): A new approach to verify and derive a transverse-fielddependent mobility model for electrons in MOS inversion layers. JEFF. Trans. Electron Devices, 36: 1117.CrossRefGoogle Scholar
  14. [14]
    Shigyo, N., Fukuda, S., Kato, K. (1989): The influence of boundary locations on wiring capacitance simulation TREE Trans. Electron Devices, ED-36: 1171.CrossRefGoogle Scholar
  15. [15]
    Shigyo, N. (2000): Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations. IEEE Trans. Electron Devices, 47: 1740.Google Scholar

Copyright information

© Springer-Verlag Wien 2001

Authors and Affiliations

  • Naoyuki Shigyo
    • 1
  1. 1.System LSI Design DivisionToshiba Corporation Semiconductor Company STE BldKasama,Sakae-ku,YokohamaJapan

Personalised recommendations