Eurocode ’92 pp 395-403 | Cite as

VLSI Implementation of a Fractal Image Compression Algorithm

  • R. Creutzburg
  • W. Geiselmann
  • F. Heyl
Part of the International Centre for Mechanical Sciences book series (CISM, volume 339)


In this paper we describe a VLSI implementation of a lossy image compression [1] algorithm given in [2]. The chip was designed using the full—custom VLSI CAD system ISIS and was performed in the hardware description language HDL of this system on transistor level [3, 4, 5]. The chip area is about 1 mm2 using a 2μ-CMOS technology.


Fractal Dimension Boolean Function Clock Cycle Image Compression VLSI Design 


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Copyright information

© Springer-Verlag Wien 1993

Authors and Affiliations

  • R. Creutzburg
    • 1
  • W. Geiselmann
    • 1
  • F. Heyl
    • 1
  1. 1.University of KarlsruheKarlsruheGermany

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