Abstract
In this paper we describe a VLSI implementation of a lossy image compression [1] algorithm given in [2]. The chip was designed using the full—custom VLSI CAD system ISIS and was performed in the hardware description language HDL of this system on transistor level [3, 4, 5]. The chip area is about 1 mm2 using a 2μ-CMOS technology.
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© 1993 Springer-Verlag Wien
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Creutzburg, R., Geiselmann, W., Heyl, F. (1993). VLSI Implementation of a Fractal Image Compression Algorithm. In: Camion, P., Charpin, P., Harari, S. (eds) Eurocode ’92. International Centre for Mechanical Sciences, vol 339. Springer, Vienna. https://doi.org/10.1007/978-3-7091-2786-5_33
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DOI: https://doi.org/10.1007/978-3-7091-2786-5_33
Publisher Name: Springer, Vienna
Print ISBN: 978-3-211-82519-8
Online ISBN: 978-3-7091-2786-5
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