Skip to main content

Scalability of FinFETs and Unstrained-Si/Strained-Si FDSOI-MOSFETs

  • Conference paper
Book cover Simulation of Semiconductor Processes and Devices 2004

Abstract

Full—band Monte Carlo simulations are performed for n—type FinFETs as well as for unstrained—Si and strained—Si fully—depleted (FD) SOI-MOSFETs. Gate lengths of 50 nm down to 10 nm are considered, and a fixed off—current of 100 nA/μzm is in each case ensured by adjusting the silicon film thickness. The FinFET shows the best scaling trend, but the strained-Si FDSOI-MOSFET always involves the largest absolute value for the on—current. However, the on—current decreases upon scaling to 10 nm which might stem from a larger influence of surface roughness scattering in thin Si films affecting most strongly quasi—ballistic transport in strained Si. The feature of a decreasing current is found to be absent in drift—diffusion simulation because this approach does not include quasi—ballistic transport.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J.-S. Goo et al., IEEE Electron Device Lett. 24, 351 (2003).

    Article  Google Scholar 

  2. T. Sanuki et al., IEDM Tech. Dig., 65 (2003).

    Google Scholar 

  3. B. Yu et al., IEDM Tech. Dig., 251 (2002).

    Google Scholar 

  4. J. Kedzierski et al., IEEE Trans. Electron Devices 50, 952 (2003).

    Article  Google Scholar 

  5. R. Chau et al., IEDM Tech. Dig., 621 (2001).

    Google Scholar 

  6. T. S. Drake et al., Appl. Phys. Lett. 83, 875 (2003).

    Article  Google Scholar 

  7. K. Rim et al., IEDM Tech. Dig., 49 (2003).

    Google Scholar 

  8. J. D. Bude, Proc. SISPAD, 23 (2000).

    Google Scholar 

  9. F. M. Bufler and W. Fichtner, IEEE Trans. Electron Devices 50, 278 (2003).

    Article  Google Scholar 

  10. C. Jungemann and B. Meinerzhagen, in Proc. ESSDERC, 9 (2003).

    Google Scholar 

  11. R. J. Luyken et al., Solid-State Electron. 47, 1199 (2003).

    Article  Google Scholar 

  12. A. Svizhenko and M. P. Anantram, IEEE Trans. Electron Devices 50, 1459 (2003).

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Wien

About this paper

Cite this paper

Bufler, F.M., Schenk, A., Fichtner, W. (2004). Scalability of FinFETs and Unstrained-Si/Strained-Si FDSOI-MOSFETs. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_44

Download citation

  • DOI: https://doi.org/10.1007/978-3-7091-0624-2_44

  • Publisher Name: Springer, Vienna

  • Print ISBN: 978-3-7091-7212-4

  • Online ISBN: 978-3-7091-0624-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics