Abstract
We demonstrate the applicability of three-dimensional process simulation and show its benefit for the development of modern semiconductor technology. Therefore we have performed a process simulation for a Cay wood-EEPROM memory cell, followed by the extraction of the coupling capacitance. Such a kind of analysis allows to optimize the layout of the EEPROM memory cell as well as the process parameters. Additionally we show that it is sufficient for the simulation of various process steps to apply simplified empirical models without loosing accuracy in the extracted parameters since the physical behavior of deposition and etching processes is often empirically well characterized within a certain process window.
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© 2004 Springer-Verlag Wien
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Hössinger, A., Minixhofer, R., Selberherr, S. (2004). Full Three-Dimensional Analysis of a Non-Volatile Memory Cell. In: Wachutka, G., Schrag, G. (eds) Simulation of Semiconductor Processes and Devices 2004. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0624-2_31
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DOI: https://doi.org/10.1007/978-3-7091-0624-2_31
Publisher Name: Springer, Vienna
Print ISBN: 978-3-7091-7212-4
Online ISBN: 978-3-7091-0624-2
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