Zusammenfassung
Pipelining ist eine Implementierungsmethode, bei der mehrere Befehle überlappt abgearbeitet werden. Heute ist Pipelining eine Schlüsselimplementierungsmethode, um schnelle Prozessoren zu realisieren.
Es ist wirklich ein Problem für drei Pfeifen (three-pipe problem).
Sir Arthur Conan Doyle, The Adventures of Sherlock Holmes
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
Literaturquellen
Agerwala, T. and J. Cocke [1987]. “High performance reduced instruction set processors,” IBM Tech. Rep. (March).
Anderson, D. W., F. J. Sparacio, and R. M. Tomasulo [1967]. “The IBM 360 Model 91: Machine philosophy and instruction handling,” IBM J. of Research and Development 11:1 (January) 8–24.
Bakoglu, H. B., G. F. Grohoski, L. E. Thatcher, J. A. Kahle, C. R. Moore, D. P. Tuttle, W. E. Maule, W. R. Hardell, D. A. Hicks, M. Nguyen Phu, R. K. Montoye, W. T. Glover , and S. Dhawan [1989]. “IBM second-generation Risc machine organization,” Proc. Int’l Conf. on Computer Design, IEEE (October) Rye, N.Y., 138–142.
Bloch, E. [1959]. “The engineering design of the Stretch computer,” Proc. Fall Joint Computer Conf., 48–59.
Bucholtz, W. [1962]. Planning a Computer System: Project Stretch, McGraw-Hill, New York.
Charlesworth, A. E. [1981]. “An approach to scientific array processing: The architecture design of the Ap-120B/Fps-164 family,” Computer 14:12 (December) 12–30.
Chen, T. C. [1980]. “Overlap and parallel processing” in Introduction to Computer Architecture, H. Stone, ed., Science Research Associates, Chicago, 427–486.
Clark, D. W. [1987]. “Pipelining and performance in the Vax 8800 processor,” Proc. Second Conf on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (March), Palo Alto, Calif., 173–177.
Colwell, R. P., R. P. Nix, J. J. O’Donnell, D. B. Papworth, and B. K. Rodman [1987]. “A VLIW architecture for a trace scheduling compiler,” Proc. Second Conf on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (March), Palo Alto, Calif., 180–192.
Davidson, E. S. [1971]. “The design and control of pipelined function generators,” Proc. Conf. on Systems, Networks, and Computers, IEEE (January), Oaxtepec, Mexico, 19–21.
Davidson, E. S., A. T. Thomas, L. E. Shar, and J. H. Patel [1975]. “Effective control for pipelined processors,” Compcon, IEEE (March), San Francisco, 181–184.
Dehnert, J. C., P. Y.-T. Hsu, and J. P. Bratt [1989]. “Overlapped loop support on the Cydra 5,” Proc. Third Conf. on Architectural Support for Programming Languages and Operating Systems (April), IEEE/ACM, Boston, 26–39.
Derosa, J., R. Glackemeyer, and T. Knight [1985]. “Design and implementation of the Vax 8600 pipeline,” Computer 18:5 (May) 38–48.
Digital Equipment Corporation [1987]. Digital Technical J. 4 (March), Hudson, Mass. (This entire issue is devoted to the Vax 8800 processor.)
Ditzel, D. R. and H. R. Mclellan [1987]. “Branch folding in the Crisp microprocessor: Reducing the branch delay to zero,” Proc. 14th Symposium on Computer Architecture (June), Pittsburgh, 2–7.
Earle, J. G. [1965]. “Latched carry-save adder,” IBM Technical Disclosure Bull. 7 (March) 909–910.
Ellis, J. R., [1986]. Bulldog: A Compiler for Vliw Architectures, The Mit Press,1986.
Emer, J. S. and D. W. Clark [1984]. “A characterization of processor performance in the Vax-11/780,” Proc. 11th Symposium on Computer Architecture (June), Ann Arbor, Mich., 301–310.
Fisher, J. A. [1981]. “Trace Scheduling: A Technique for Global Microcode Compaction,” IEEE Trans. on Computers 30:7 (July), 478–490.
Fisher, J. A. [1983]. “Very long instruction word architectures and Eli-512,” Proc. Tenth Symposium on Computer Architecture (June), Stockholm, Sweden., 140–150.
Fisher J. A., J. R. Ellis, J. C. Ruttenberg, and A. Nicolau [1984]. “Parallel processing: A smart compiler and a dumb machine,” Proc. Sigplan Conf. on Compiler Construction (June), Palo Alto, Ca, 11–16.
Foster, C. C. and E. M. Riseman [1972]. “Percolation of code to enhance parallel dispatching and execution,” IEEE Trans. on Computers C-21:12 (December) 1411–1415.
Gibbons, P. B. and S. S. Muchnik [1986]. “Efficient Instruction Scheduling for a Pipeline-D Processor,” Sigplan ’86 Symposium on Compiler Construction, A Cm (June), Palo Alto, Ca, 11–16.
Gross, T. R. [1983]. Code Optimization of Pipeline Constraints, Ph.D. Thesis (December), Computer Systems Lab., Stanford Univ.
Hennessy, J. L. and T. R. Gross [1983]. “Postpass code optimization of pipeline constraints,” ACM Trans. on Programming Languages and Systems 5:3 (July) 422–448
Hwu, W.-M. and Y. Patt [1986]. “HPSm, a high performance restricted data flow architecture having minimum functionality,” Proc. 13th Symposium on Computer Architecture (June), Tokyo, 297–307.
IBM [1990]. “The IBM Risc System/6000 processor,” collection of papers, IBM Jour, of Research and Development 34:1, (January), 119 pages.
Jouppi N. P. and D. W. Wall [1989]. “Available instruction-level parallelism for superscalar and superpipelined machines,” Proc. Third Conf. on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (April), Boston, 272–282.
Keller R. M. [1975]. “Look-ahead processors,” ACM Computing Surveys 7:4 (December) 177–195.
Kogge, P. M. [1981]. The Architecture of Pipeline-D Computers, McGraw-Hill, New York.
Kunkel, S. R. and J. E. Smith [1986]. “Optimal pipelining in supercomputers,” Proc. 13th Symposium on Computer Architecture (June), Tokyo, 404–414.
Lam, M. [1988]. “Software pipelining: An effective scheduling technique for Vliw machines,” Sigplan Conf. on Programming Language Design and Implementation, ACM (June), Atlanta, Ga., 318–328.
Mcfarling, S. and J. Hennessy [1986]. “Reducing the cost of branches,” Proc. 13th Symposium on Computer Architecture (June), Tokyo, 396–403.
Nicolau, A. and J. A. Fisher [1984]. “Measuring the parallelism available for very long instruction work architectures,” IEEE Trans. on Computers C-33:11 (November) 968–976.
Ramamoorthy, C. V. and H. F. Li [1977]. “Pipeline architecture,” ACM Computing Surveys 9:1 (March) 61–102.
Rymarczyk, J. [1982]. “Coding guidelines for pipelined processors,” Proc. Symposium on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (March), Palo Alto, Calif., 12–19.
Sites, R. [1979]. Instruction Ordering for the Cray-1 Computer, Tech. Rep. 78-Cs-023 (July), Dept. of Computer Science, Univ. of Calif., San Diego.
Smith, A. and J. Lee [1984]. “Branch prediction strategies and branch target buffer design,” Computer 17:1 (January) 6–22.
Smith, J. E. [1981]. “A study of branch prediction strategies,” Proc. Eighth Symposium on Computer Architecture (May), Minneapolis, 135–148.
Smith, J. E. [1984]. “Decoupled access/execute computer architectures,” ACM Trans. on Computer Systems 2:4 (November), 289–308.
Smith, J. E. [1989]. “Dynamic instruction scheduling and the Astronautics Zs-1,” Computer 22:7 (July) 21–35.
Smith, J. E. and A. R. Plezkun [1988]. “Implementing precise interrupts in pipelined processors,” IEEE Trans. on Computers 37:5 (May) 562–573.
Smith, J. E., G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, J. P. Laudon [1987]. “The Zs-1 central processor,” Proc. Second Conf. on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (March), Palo Alto, Calif., 199–204.
Smith, M. D., M. Johnson, and M. A. Horowitz [1989]. “Limits on multiple instruction issue,” Proc. Third Conf. on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (April), Boston, Mass., 290–302.
Sohi, G. S., and S. Vajapeyam [1989]. “Tradeoffs in instruction format design for horizontal architectures,” Proc. Third Conf. on Architectural Support for Programming Languages and Operating Systems, IEEE/ACM (April), Boston, Mass. 15–25.
Thorlin, J. F. [1967]. “Code generation for Pie (parallel instruction execution) computers,” Spring Joint Computer Conf. (April), Atlantic City, N.J.
Thornton, J. E. [1964]. “Parallel operation in the Control Data 6600,” Proc. Fall Joint Computer Conf. 26, 33–40.
Thornton, J. E. [1970]. Design of a Computer, the Control Data 6600, Scott, Foresman, Glenview, Ill.
Tjaden, G. S. and M. J. Flynn [1970]. “Detection and parallel execution of independent instructions,” IEEE Trans. on Computers C-19:10 (October) 889–895.
Tomasulo, R. M. [1967]. “An efficient algorithm for exploiting multiple arithmetic units,” IBM J. of Research and Development 11:1 (January) 25–33.
Troiani, M., S. S. Chdng, N. N. Quaynor, J. E. Bloem, and F. C. Colon Osorio [1985]. “The Vax 8600 I Box, a pipelined implementation of the Vax architecture,” Digital Technical J. 1 (August) 4–19.
Weiss, S. and J. E. Smith [1984]. “Instruction issue logic for pipelined supercomputers,” Proc. 11th Symposium on Computer Architecture (June), Ann Arbor, Mich., 110–118.
Weiss, S. and J. E. Smith [1987]. “A study of scalar compilation techniques for pipelined supercomputers,” Proc. Second Conf. on Architectural Support for Programming Languages and Operating Systems (March), IEEE/ACM, Palo Alto, Calif, 105–109
Rights and permissions
Copyright information
© 1994 Springer Fachmedien Wiesbaden
About this chapter
Cite this chapter
Hennessy, J.L., Patterson, D.A. (1994). Pipelining. In: Rechnerarchitektur. Lehrbuch Informatik. Vieweg+Teubner Verlag, Wiesbaden. https://doi.org/10.1007/978-3-663-13953-9_6
Download citation
DOI: https://doi.org/10.1007/978-3-663-13953-9_6
Publisher Name: Vieweg+Teubner Verlag, Wiesbaden
Print ISBN: 978-3-528-05173-0
Online ISBN: 978-3-663-13953-9
eBook Packages: Springer Book Archive