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Transactions on High-Performance Embedded Architectures and Compilers V pp 21–38Cite as

Programmable and Scalable Architecture for Graphics Processing Units

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Part of the book series: Lecture Notes in Computer Science ((THIPEAC,volume 11225))

Abstract

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.

In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allows more programming freedom than vector processors.

Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it a suitable target for general purpose computing on GPU APIs which have become popular in the recent years.

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Acknowledgments

This research was partially funded by the Academy of Finland, the Nokia Foundation, and Finnish Center for International Mobility (CIMO).

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Authors and Affiliations

  1. Department of Computer Architecture, Computer Science and Artificial Intelligence, Universidad Rey Juan Carlos, Móstoles, Spain

    Carlos S. de La Lama

  2. Tampere University, Tampere, Finland

    Pekka Jääskeläinen, Heikki Kultala & Jarmo Takala

Authors
  1. Carlos S. de La Lama
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  2. Pekka Jääskeläinen
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  3. Heikki Kultala
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  4. Jarmo Takala
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Corresponding author

Correspondence to Carlos S. de La Lama .

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Editors and Affiliations

  1. Politecnico di Milano, Milan, Italy

    Cristina Silvano

  2. Delft University of Technology, Delft, The Netherlands

    Koen Bertels

  3. University of Wisconsin–Madison, Madison, WI, USA

    Michael Schulte

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de La Lama, C.S., Jääskeläinen, P., Kultala, H., Takala, J. (2019). Programmable and Scalable Architecture for Graphics Processing Units. In: Silvano, C., Bertels, K., Schulte, M. (eds) Transactions on High-Performance Embedded Architectures and Compilers V. Lecture Notes in Computer Science(), vol 11225. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-58834-5_2

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  • DOI: https://doi.org/10.1007/978-3-662-58834-5_2

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  • Print ISBN: 978-3-662-58833-8

  • Online ISBN: 978-3-662-58834-5

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