• Zhiqiang LiEmail author
Part of the Springer Theses book series (Springer Theses)


With continuous expansion of semiconductor consumption market, integrate circuit (IC) has developed rapidly in the past 40 years. As the foundation of information industry, IC has played an irreplaceable role in commerce, national defense, communication, and daily life. Meanwhile, the information industry based on IC has created remarkable economic benefits, which has exceeded that of traditional industries such as auto, fossil oil, and steel industry. Nowadays, IC is moving toward higher integration density, larger circuit speed, and lower power consumption, and all this will hasten humanity’s advance into information age.


Schottky Barrier Height Specific Contact Resistivity High Integration Density Effective Oxide Thickness Device Gate Length 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Moore GE (1975) Progress in digital integrated electronics. In: IEDM technical digestGoogle Scholar
  2. 2.
    Moore GE (1998) Cramming more components onto integrated circuits (Reprinted from Electronics, pp 114–117, April 19, 1965). Proc IEEE 86:82–85CrossRefGoogle Scholar
  3. 3.
    International technology roadmap for semiconductors. 2013 edn. Available: (
  4. 4.
    Skotnicki T, Hutchby JA, King TJ, Wong HSP, Boeuf F (2005) The end of CMOS scaling. IEEE Circuits Dev 21:16–26Google Scholar
  5. 5.
    Ieong M, Doris B, Kedzierski J, Rim K, Yang M (2004) Silicon device scaling to the sub-10-nm regime. Science 306:2057–2060ADSCrossRefGoogle Scholar
  6. 6.
    Auth C, Allen C, Blattner A, Bergstrom D, Brazier M, Bost M, et al (2012) A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: 2012 symposium on VLSI technology, VLSIT, pp 131–132Google Scholar
  7. 7.
    Basak S, Nagaraj S, Nahar RK (2013) Simulation and optimization of channel mobility in high-k/metal gate nanoscale MOSFETs. In: Proceedings of international conference on VLSI, communication, advanced devices, signals & systems and networking, VCASAN-2013, pp 231–240Google Scholar
  8. 8.
    Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al (2003) A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: 2003 IEEE international electron devices meeting, technical digest, pp 978–980Google Scholar
  9. 9.
    Saraswat K (2007) High mobility materials and novel device structures for advanced CMOS technology. Presented at the IEDM short courseGoogle Scholar
  10. 10.
    Saraswat KC, Chui CO, Kim D, Krishnamohan T, Pethe A (2006) High mobility materials and novel device structures for high performance nanoscale MOSFETs. In: 2006 international electron devices meeting, vols 1 and 2, pp 395–398Google Scholar
  11. 11.
    Houssa M, Ye P, Heyns M (2013) High mobility channels. In: High permittivity gate dielectric materials. Springer, Berlin, pp 425–457Google Scholar
  12. 12.
    Schwierz F (2010) Graphene transistors. Nat Nanotechnol 5:487–496ADSCrossRefGoogle Scholar
  13. 13.
    Franklin AD, Luisier M, Han S-J, Tulevski G, Breslin CM, Gignac L et al (2012) Sub-10 nm carbon nanotube transistor. Nano Lett 12:758–762ADSCrossRefGoogle Scholar
  14. 14.
    Sun Y, Majumdar A, Cheng C-W, Kim Y-H, Rana U, Martin R, et al (2013) Self-aligned III–V MOSFETs: towards a CMOS compatible and manufacturable technology solution. In: 2013 IEEE international electron devices meeting, IEDM, pp 2.7.1–2.7.4Google Scholar
  15. 15.
    Trumbore FA (1960) Solid solubilities of impurity elements in germanium and silicon. Bell Syst Tech J 39:205–233CrossRefGoogle Scholar
  16. 16.
    Chui CO, Kulig L, Moran J, Tsai W, Saraswat KC (2005) Germanium n-type shallow junction activation dependences. Appl Phys Lett 87:091909ADSCrossRefGoogle Scholar
  17. 17.
    Deal M, Plummer J, Griffin P (2000) Silicon VLSI technology fundamentals, practice and modeling. Prentice Hall, Upper Saddle RiverGoogle Scholar
  18. 18.
    Kim J, Bedell SW, Sadana DK (2011) Improved germanium n+/p junction diodes formed by coimplantation of antimony and phosphorus. Appl Phys Lett 98:082112–082112-3Google Scholar
  19. 19.
    Chui CO, Gopalakrishnan K, Griffin PB, Plummer JD, Saraswat KC (2003) Activation and diffusion studies of ion-implanted p and n dopants in germanium. Appl Phys Lett 83:3275–3277ADSCrossRefGoogle Scholar
  20. 20.
    Trumbore FA (1960) Solid solubilities of impurity elements in germanium and silicon*. Bell Syst Tech J 39:205–233CrossRefGoogle Scholar
  21. 21.
    Thareja G, Chopra S, Adams B, Patil N, Ta Y, Porshnev P, et al (2010) Ultra shallow junctions with high dopant activation and GeO2 interfacial layer for gate dielectric in germanium MOSFETs. In: Device research conference, DRC, 2010, pp 23–24Google Scholar
  22. 22.
    Jamil M, Mantey J, Onyegam EU, Carpenter GD, Tutuc E, Banerjee SK (2011) High-performance Ge nMOSFETs with n(+)-p junctions formed by ”spin-on dopant”. IEEE Electron Dev Lett 32:1203–1205ADSCrossRefGoogle Scholar
  23. 23.
    Chui CO, Kim H, McIntyre PC, Saraswat KC (2003) A germanium NMOSFET process integrating metal gate and improved hi-kappa dielectrics. In: 2003 IEEE international electron devices meeting, technical digest, pp 437–440Google Scholar
  24. 24.
    Wündisch C, Posselt M, Schmidt B, Heera V, Schumann T, Mücklich A et al (2009) Millisecond flash lamp annealing of shallow implanted layers in Ge. Appl Phys Lett 95:252107ADSCrossRefGoogle Scholar
  25. 25.
    Thareja G, Liang J, Chopra S, Adams B, Patil N, Cheng SL, et al (2010) High performance germanium N-MOSFET with antimony dopant activation beyond 1 × 10(20) cm(-3). In: 2010 international electron devices meeting—technical digestGoogle Scholar
  26. 26.
    Kuzum D, Krishnamohan T, Nainani A, Sun Y, Pianetta PA, Wong HSP, et al (2009) Experimental demonstration of high mobility Ge NMOS. In: 2009 IEEE international electron devices meeting, pp 420–423Google Scholar
  27. 27.
    Yu HY, Cheng SL, Griffin PB, Nishi Y, Saraswat KC (2009) Germanium in situ doped epitaxial growth on Si for high-performance n(+)/p-junction diode. IEEE Electron Dev Lett 30:1002–1004ADSCrossRefGoogle Scholar
  28. 28.
    Dimoulas A, Tsipas P, Sotiropoulos A, Evangelou EK (2006) Fermi-level pinning and charge neutrality level in germanium. Appl Phys Lett 89:252110–252110-3Google Scholar
  29. 29.
    Nishimura T, Kita K, Toriumi A (2007) Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface. Appl Phys Lett 91:123123–123123-3Google Scholar
  30. 30.
    Martens K, Firrincieli A, Rooyackers R, Vincent B, Loo R, Locorotondo S, et al (2010) Record low contact resistivity to n-type Ge for CMOS and memory applications. In: 2010 international electron devices meeting—technical digestGoogle Scholar
  31. 31.
    Bin Y, Lin JYJ, Gupta S, Roy A, Shurong L, Maszara WP, et al (2012) Low-contact-resistivity nickel germanide contacts on n + Ge with phosphorus/antimony co-doping and Schottky barrier height lowering. In: 2012 international on silicon-germanium technology and device meeting, ISTDM, pp 1–2Google Scholar
  32. 32.
    Xiong SY, King TJ, Bokor J (2005) A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain. IEEE Trans Electron Dev 52:1859–1867ADSCrossRefGoogle Scholar
  33. 33.
    Connelly D, Faulkner C, Grupp DE, Harris JS (2004) A new route to zero-barrier metal source/drain MOSFETs. IEEE Trans Nanotechnol 3:98–104ADSCrossRefGoogle Scholar
  34. 34.
    Tersoff J (1984) Schottky barrier heights and the continuum of gap states. Phys Rev Lett 52:465–468ADSCrossRefGoogle Scholar
  35. 35.
    Nishimura T, Kita K, Toriumi A (2008) A significant shift of Schottky barrier heights at strongly pinned metal/germanium interface by inserting an ultra-thin insulating film. Appl Phys Exp 1:051406ADSCrossRefGoogle Scholar
  36. 36.
    Zhou Y, Ogawa M, Han X, Wang KL (2008) Alleviation of Fermi-level pinning effect on metal/germanium interface by insertion of an ultrathin aluminum oxide. Appl Phys Lett 93:202105–202105-3Google Scholar
  37. 37.
    Li Zhiqiang, An Xia, Yun Quanxin, Lin Meng, Zhang Xing, Huang Ru (2012) Tuning Schottky Barrier height in metal/n-type germanium by inserting an ultrathin yttrium oxide film. ECS Solid State Lett 1(4):Q33–Q34CrossRefGoogle Scholar
  38. 38.
    Lin JYJ, Roy AM, Nainani A, Sun Y, Saraswat KC (2011) Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height. Appl Phys Lett 98Google Scholar
  39. 39.
    Zhou Y, Han W, Yong W, Xiu F, Zou J, Kawakami RK, et al (2010) Investigating the origin of Fermi level pinning in Ge Schottky junctions using epitaxially grown ultrathin MgO films. Appl Phys Lett 96:102103–102103-3Google Scholar
  40. 40.
    Lieten R, Degroote S, Kuijk M, Borghs G (2008) Ohmic contact formation on n-type Ge. Appl Phys Lett 92:022106–022106-3Google Scholar
  41. 41.
    Kobayashi M, Kinoshita A, Saraswat K, Wong HSP, Nishi Y (2009) Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application. J Appl Phys 105:023702–023702-6Google Scholar
  42. 42.
    Thathachary AV, Bhat KN, Bhat N, Hegde MS (2010) Fermi level depinning at the germanium Schottky interface through sulfur passivation. Appl Phys Lett 96:152108–152108-3Google Scholar
  43. 43.
    Tong Y, Liu B, Lim PSY, Yeo Y-C (2012) Selenium segregation for effective Schottky barrier height reduction in NiGe/n-Ge contacts. IEEE Electron Dev Lett 33:773–775ADSCrossRefGoogle Scholar
  44. 44.
    Ikeda K, Yamashita Y, Sugiyama N, Taoka N, Takagi S (2006) Modulation of NiGe/Ge Schottky barrier height by sulfur segregation during Ni germanidation. Appl Phys Lett 88Google Scholar
  45. 45.
    Kaxiras E (1991) Semiconductor-surface restoration by valence-mending adsorbates—application to Si(100)-S and Si(100)-Se. Phys Rev B 43:6824–6827ADSCrossRefGoogle Scholar
  46. 46.
    Guo Y, An X, Huang R, Fan CH, Zhang X (2010) Tuning of the Schottky barrier height in NiGe/n-Ge using ion-implantation after germanidation technique. Appl Phys Lett 96Google Scholar
  47. 47.
    Alptekin E, Ozturk MC (2009) Tuning of the nickel silicide Schottky barrier height on p-type silicon by indium implantation. IEEE Electron Dev Lett 30:1272–1274ADSCrossRefGoogle Scholar
  48. 48.
    Sinha M, Chor EF, Yeo YC (2008) Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation. Appl Phys Lett 92Google Scholar
  49. 49.
    Mueller M, Zhao Q, Urban C, Sandow C, Buca D, Lenk S et al (2008) Schottky-barrier height tuning of NiGe/n-Ge contacts using As and P segregation. Mater Sci Eng, B 154:168–171CrossRefGoogle Scholar
  50. 50.
    Wong HS, Chan L, Sainudra G, Yeo YC (2007) Sub-0.1-eV effective Schottky-barrier height for NiSi on n-type Si (100) using antimony segregation. IEEE Electron Dev Lett 28:703–705ADSCrossRefGoogle Scholar
  51. 51.
    Hsu S-L, Chien C-H, Ming-Jui Y, Huang R-H, Leu C-C, Shen S-W, et al (2005) Study of thermal stability of nickel monogermanide on single- and polycrystalline germanium substrates. Appl Phys Lett 86:251906–251906-3Google Scholar
  52. 52.
    Zhu S, Nakajima A (2005) Annealing temperature dependence on nickel–germanium solid-state reaction. Jpn J Appl Phys 44:L753ADSCrossRefGoogle Scholar
  53. 53.
    Lee K, Liew S, Chua S, Chi D, Sun H, Pan X (2004) Formation and morphology evolution of nickel germanides on Ge (100) under rapid thermal annealing. In: MRS proceedings, p C2.4Google Scholar
  54. 54.
    Shiyang Z, Yu MB, Lo GQ, Kwong DL (2007) Enhanced thermal stability of nickel germanide on thin epitaxial germanium by adding an ultrathin titanium layer. Appl Phys Lett 91:051905–051905-3Google Scholar
  55. 55.
    Park K, Lee B, Lee D, Ko D-H, Kwak K, Yang C-W et al (2007) A study on the thermal stabilities of the NiGe and Ni1−xTaxGe systems. J Electrochem Soc 154:H557–H560CrossRefGoogle Scholar
  56. 56.
    Zhang Y-Y, Oh J, Li S-G, Jung S-Y, Park K-Y, Shin H-S et al (2009) Ni germanide utilizing ytterbium interlayer for high-performance Ge MOSFETs. Electrochem Solid-State Lett 12:H18–H20CrossRefGoogle Scholar
  57. 57.
    Zhang Y-Y, Oh J, Li S-G, Jung S-Y, Park K-Y, Lee G-W et al (2010) Improvement of thermal stability of Ni germanide using a Ni–Pt (1 %) alloy on Ge-on-Si substrate for nanoscale Ge MOSFETs. IEEE Trans Nanotechnol 9:258–263ADSCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  1. 1.Institute of MicroelectronicsPeking UniversityBeijingChina

Personalised recommendations